M4-96/96-15YC Lattice, M4-96/96-15YC Datasheet - Page 20

• Manufacturer Part Number: M4-96/96-15YC
• Description: CPLD - Complex Programmable Logic Devices HI PERF E2CMOS PLD
• Manufacturer: Lattice

Specifications of M4-96/96-15YC

• Product Category: CPLD - Complex Programmable Logic Devices
• Number Of Macrocells: 96
• Maximum Operating Frequency: 55.6 MHz, 83.3 MHz
• Delay Time: 15 ns
• Number Of Programmable I/os: 224
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Package / Case: PQFP-144
• Mounting Style: SMD/SMT
• Number Of Product Terms Per Macro: 20
• Factory Pack Quantity: 24
• Supply Voltage - Max: 5.25 V
• Supply Voltage - Min: 4.75 V

ispMACH 4A TIMING MODEL
The primary focus of the ispMACH 4A timing model is to accurately represent the timing in a ispMACH
4A device, and at the same time, be easy to understand. This model accurately describes all combinatorial
and registered paths through the device, making a distinction between internal feedback and external
feedback. A signal uses internal feedback when it is fed back into the switch matrix or block without having
to go through the output buffer. The input register specifications are also reported as internal feedback.
When a signal is fed back into the switch matrix after having gone through the output buffer, it is using
external feedback.
The parameter, t
I/O pad. If a signal goes to the internal feedback rather than to the I/O pad, the parameter designator is
followed by an “i”. By adding t
example, t
in Figure 15. Refer to the application note entitled MACH 4 Timing and High Speed Design for a more detailed
discussion about the timing parameters.
SPEEDLOCKING FOR GUARANTEED FIXED TIMING
The ispMACH 4A architecture allows allocation of up to 20 product terms to an individual macrocell with
the assistance of an XOR gate without incurring additional timing delays.
The design of the switch matrix and PAL blocks guarantee a fixed pin-to-pin delay that is independent of
the logic required by the design. Other competitive CPLDs incur serious timing delays as product terms
expand beyond their typical 4 or 5 product term limits. Speed and SpeedLocking combine to give designs
easy access to the performance required in today’s designs.
20
BLK CLK
IN
PD
= t
PDi
BUF
t
t
t
t
t
t
t
t
SIRS
HIRS
SIL
HIL
SIRZ
HIRZ
SILZ
HILZ
INPUT LATCH
INPUT REG/
, is defined as the time it takes to go from feedback through the output buffer to the
+ t
BUF
t
t
t
t
PDILi
ICOSi
IGOSi
PDILZi
. A diagram representing the modularized ispMACH 4A timing model is shown
Q
BUF
Central
Switch
Matrix
to this internal parameter, the external parameter is derived. For
Figure 15. ispMACH 4A Timing Model
ispMACH 4A Family
t
PL
(External Feedback)
(Internal Feedback)
COMB/DFF/TFF/
t
t
t
t
t
t
LATCH/SR*/JK*
SS(T)
SA(T)
H(S/A)
S(S/A)L
H(S/A)L
SRR
*emulated
S/R
t
t
t
t
t
PDi
PDLi
CO(S/A)i
GO(S/A)i
SRi
Q
t
BUF
t
t
ER
EA
t
SLW
17466G-025
OUT