MAX11359AETL Maxim Integrated, MAX11359AETL Datasheet - Page 58

• Manufacturer Part Number: MAX11359AETL
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX11359AETL

• Number Of Channels: 10
• Architecture: Sigma-Delta
• Conversion Rate: 10 SPs to 512 SPs
• Resolution: 16 bit
• Input Type: Differential
• Interface Type: 4-Wire Serial, Microwire, QSPI, SPI
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Power Dissipation: 2051.3 mW
• Number Of Converters: 1
• Voltage Reference: 1.251 V 1.996 V, 2.422 V

16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
• With the SLEEP or SLEEP function deasserted on
• With the SLEEP or SLEEP function deasserted,
• With the SLEEP or SLEEP function deasserted, the
A wake-up event, such as an assertion of a UPIO con-
figured as WU or a time-of-day alarm causes the
MAX11359A to exit sleep mode, if in sleep mode. A
wake-up event in normal mode results only in a wake-up
event being recorded in the STATUS register.
The RESET output pulls low for any one of the following
cases: power-on reset, DVDD monitor trips and RSTE =
0, watchdog timer expires, crystal oscillator is attached,
and 32kHz clock not ready.
The RESET output can be turned off through the RSTE
bit in the PS_VMONS register, causing DVDD low sup-
ply voltage events to issue an interrupt or poll through
the LDVD status bit. This allows brownout detection
µCs that operate with V
UPIO outputs can be driven to AVDD levels in systems
with separate AVDD and DVDD supplies. Disable the
charge-pump doubler by setting CPE = 0 in the
PS_VMONS register, and connect the system’s analog
MAX11359A
Figure 20. ADC Unipolar Transfer Function
58
UPIO, clear the SHDN bit by writing to the normal-
mode register address control byte.
assert WU or WU (wake-up) function on UPIO.
day alarm triggers.
1111 1111 1111 1100
0000 0000 0000 0011
1111 1111 1111 1111
1111 1111 1111 1110
1111 1111 1111 1101
0000 0000 0000 0010
0000 0000 0000 0001
0000 0000 0000 0000
Driving UPIO Outputs to AVDD Levels
0
1 LSB =
1
2
(GAIN x 65,536)
DVDD
3
V
REF
INPUT VOLTAGE (LSB)
FULL-SCALE TRANSITION
< 1.8V.
V
REF
/GAIN
65,533
Wake-Up
65,535
RESET
supply to AVDD and CPOUT. Setting UPIO outputs to
drive to CPOUT results in AVDD-referenced logic levels.
The AVDD supply voltage can be measured with the
ADC by reversing the normal input and reference sig-
nal s. The REF voltage is applied to one multiplexer
input, and AGND is selected in the other. The AVDD
signal is then switched in as the ADC reference voltage
and a conversion is performed. The AVDD value can
then be calculated directly as:
where V
is the PGA gain before the ADC, and N is the ADC
result. Note the AVDD voltage must be greater than the
gained-up REF voltage (V
measurement must be done in unipolar mode.
Figure 21. ADC Bipolar Transfer Function
Figure 22. DAC Unipolar Output Circuit
0111 1111 1111 1111
0111 1111 1111 1110
0111 1111 1111 1101
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1000 0000 0000 0010
1000 0000 0000 0001
1000 0000 0000 0000
REF
V
AVDD
is the reference voltage for the ADC, Gain
-32,768
1 LSB =
Supply Voltage Measurement
= (V
DAC A
-32,766
MAX11359A
V
(GAIN x 65,536)
REF
REF
/GAIN
V
REF
INPUT VOLTAGE (LSB)
x Gain x 65536)/N
AVDD
-1
x 2
0
> V
+1
REF
V
FBA
REF
+32,765
/GAIN
x Gain). This
Maxim Integrated
OUTA
+32,767