MAX1133BEAP Maxim Integrated, MAX1133BEAP Datasheet - Page 8

• Manufacturer Part Number: MAX1133BEAP
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1133BEAP

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 200 KSPs
• Resolution: 16 bit
• Input Type: Single-Ended
• Snr: 92 dB
• Interface Type: Serial
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-20
• Maximum Power Dissipation: 640 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: Internal or External

The MAX1132/MAX1133 analog-to-digital converters
(ADCs) use a successive-approximation technique and
input track/hold (T/H) circuitry to convert an analog sig-
nal to a 16-bit digital output. The MAX1132/MAX1133
easily interfaces to microprocessors (µPs). The data
bits can be read either during the conversion in exter-
nal clock mode or after the conversion in internal clock
mode.
In addition to a 16-bit ADC, the MAX1132/MAX1133
include an input scaler, an internal digital microcon-
troller, calibration circuitry, an internal clock generator,
and an internal bandgap reference. The input scaler for
the MAX1132 enables conversion of input signals rang-
ing from 0 to +12V (unipolar input) or ±12V (bipolar
input). The MAX1133 accepts 0 to +4.096V (unipolar
input) or ±4.096V (bipolar input). Input range selection
is software controlled.
To minimize linearity, offset, and gain errors, the
MAX1132/MAX1133 have on-demand software calibra-
tion. Initiate calibration by writing a Control-Byte with bit
M1 = 0, and bit M0 = 1 (see Table 1). Select internal or
external clock for calibration by setting the INT/EXT bit
in the Control Byte. Calibrate the MAX1132/MAX1133
with the clock used for performing conversions.
Offsets resulting from synchronous noise (such as the
conversion clock) are canceled by the MAX1132/
MAX1133’s calibration circuitry. However, because the
magnitude of the offset produced by a synchronous
signal depends on the signal’s shape, recalibration
may be appropriate if the shape or relative timing of the
16-Bit ADC, 200ksps, 5V Single-Supply
with Reference
8
PIN
13
14
15
16
17
18
19
20
_______________________________________________________________________________________
NAME
DGND
AGND
SCLK
DV
CREF
DIN
AIN
CS
DD
Serial Data Clock Input. Serial data on DIN is loaded on the rising edge of SCLK, and serial data is updated
on DOUT on the falling edge of SCLK. In external clock mode, SCLK sets the conversion speed.
Digital Ground. Connect to pin 5.
Digital Supply. 5V ±5%. Bypass DV
Serial Data Input. Serial data on DIN is latched on the rising edge of SCLK.
Chip-Select Input. Drive CS low to enable the serial interface. When CS is high, DOUT is high impedance.
In external clock mode, SSTRB is high impedance when CS is high.
Reference Buffer Bypass. Bypass CREF to AGND (pin 3) with 1µF.
Analog Ground. Connect pin 19 to pin 3.
Analog Input
Detailed Description
Calibration
DD
to DGND (pin 14) with a 0.1µF capacitor.
clock or other digital signals change, as might occur if
more than one clock signal or frequency is used.
The MAX1132/MAX1133 have an input scaler which
allows conversion of true bipolar input voltages while
operating from a single +5V supply. The input scaler
attenuates and shifts the input as necessary to map the
external input range to the input range of the internal
DAC. The MAX1132 analog input range is 0 to +12V
(unipolar) or ±12V (bipolar). The MAX1133 analog input
range is 0 to +4.096V (unipolar) or ±4.096V (bipolar).
Unipolar and bipolar mode selection is configured with
bit 6 of the serial Control Byte.
Figure 1 shows the equivalent input circuit of the
MAX1132/MAX1133. The resistor network on the analog
input provides ±16.5V fault protection. This circuit limits
the current going into or out of the pin to less than 2mA.
The overvoltage protection is active, even if the device
is in a power-down mode, or if AV
The digital interface pins consist of SHDN, RST, SSTRB,
DOUT, SCLK, DIN and CS. Bringing SHDN low, places
the MAX1132/MAX1133 in its 2.5µA shutdown mode. A
logic low on RST halts the MAX1132/MAX1133 opera-
tion and returns the part to its power-on reset state.
In external clock mode, SSTRB is is low and pulses
high for one clock cycle at the start of conversion. In
internal clock mode, SSTRB goes low at the start of the
conversion and goes high to indicate the conversion is
finished.
FUNCTION
Pin Description (continued)
DD
Digital Interface
= 0.
Input Scaler