ispLSI 1032-80LJ Lattice, ispLSI 1032-80LJ Datasheet - Page 9

• Manufacturer Part Number: ispLSI 1032-80LJ
• Description: CPLD - Complex Programmable Logic Devices USE ispMACH 4000V
• Manufacturer: Lattice

Specifications of ispLSI 1032-80LJ

• Memory Type: EEPROM
• Number Of Macrocells: 128
• Maximum Operating Frequency: 100 MHz
• Delay Time: 20 ns
• Number Of Programmable I/os: 64
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Package / Case: PLCC-84
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 450
• Supply Current: 190 mA
• Supply Voltage - Max: 5.25 V
• Supply Voltage - Min: 4.75 V

1. Calculations are based upon timing specifications for the ispLSI 1032-80.
Derivations of
Derivations of
ispLSI 1032 Timing Model
Ded. In
I/O Pin
Reset
Y1,2,3
(Input)
Y0
t
t
t
19.0 ns = (2.0+ 2.0 +7.5) + (2.0) + (2.5 + 3.0)
t
t
t
19.0 ns = (4.5 + 2.0 + 5.0) + (2.0) + (2.5 + 3.0)
su
h
co
su
h
co
5.5 ns = (2.0 + 2.0 + 8.0) + (1.0) - (2.0 + 2.0 + 3.5)
4.0 ns = (2.0 + 2.0 + 7.5) + (4.5) - (2.0 + 2.0 + 8.0)
5.5 ns = (2.0 + 2.0 + 8.0) + (1.0) - (4.5 + 2.0 + 1.0)
4.0 ns = (4.5 + 2.0 + 5.0) + (4.5) - (2.0 + 2.0 + 8.0)
#55
= Logic + Reg su - Clock (min)
=
=
= Clock (max) + Reg h - Logic
=
=
= Clock (max) + Reg co + Output
=
=
= Logic + Reg su - Clock (min)
=
=
= Clock (max) + Reg h - Logic
=
=
= Clock (max) + Reg co + Output
=
=
I/O Reg Bypass
D
RST
(t
(
(t
(
Register
(t
(
(t
(
(t
(
(t
(
#20 + #28 + #44
#50 + #40 + #52
Input
#26
#20
#20 + #28 + #35
#20 + #28 + #44
#20 + #28 + #35
#50 + #40 + #52
iobp +
gy0(max) +
#21 - 25
t
t
iobp +
iobp +
iobp +
gy0(max) +
I/O Cell
su,
su,
Q
t
t
t
h and
h and
t
t
t
grp4 +
grp4 +
grp4 +
grp4 +
t
t
gco +
gco +
t
t
co from the Product Term Clock
)
co from the Clock GLB
)
t
t
t
)
)
)
)
t
20ptxor
ptck(max)
ptck(max)
+
+
20ptxor
+
+
+
+
(
(
30, 31, 32
(
(
(
(
#40
t
t
#40
Distribution
#27, 29,
Loading
#38
#39
#38
#39
#51, 52,
gcp(max)
gcp(max)
Delay
GRP 4
53, 54
GRP
Clock
#28
GRP
#50
)
)
)
) - (
) - (
) - (
) - (
)
+
+
+
+
)
)
(
(
(t
+
+
(t
#45 + #47
#45 + #47
#20 + #28 + #44
#20 + #28 + #35
#50 + #40 + #52
#20 + #28 + #35
gsu
(t
(t
gsu
)
)
gco
+
+
gh
) - (t
) - (t
(t
(t
) - (t
)
gh
gco
+
) - (t
iobp +
)
)
(t
gy0(min) +
)
#42, 43,
XOR Delays
4 PT Bypass
Control
PTs
iobp +
#34, 35, 36
Feedback
orp +
+
20 PT
44
1
(t
#33
#55
iobp +
orp +
)
)
)
)
t
8
grp4 +
t
t
RE
OE
CK
grp4 +
ob
)
t
t
t
gco +
grp4 +
ob
GLB
t
1
)
ptck(min)
Specifications ispLSI 1032
t
20ptxor
GLB Reg Bypass
t
D
RST
t
gcp(min)
20ptxor
GLB Reg
Delay
#37
#38, 39,
40, 41
)
)
)
Q
)
ORP Bypass
Delay
ORP
ORP
#46
#45
#47
#48, 49
I/O Cell
(Output)
I/O Pin