MAX1248ACEE Maxim Integrated, MAX1248ACEE Datasheet - Page 8

• Manufacturer Part Number: MAX1248ACEE
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1248ACEE

• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 133 KSPs
• Resolution: 10 bit
• Input Type: Single-Ended/Differential
• Snr: 66 dB
• Interface Type: 4-Wire (SPI, Microwire, QSPI, TMS320)
• Operating Supply Voltage: 2.7 V to 5.25 V
• Maximum Operating Temperature: + 70 C
• Package / Case: QSOP-16
• Maximum Power Dissipation: 667 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Voltage Reference: 2.5 V

The MAX1248/MAX1249 analog-to-digital converters
(ADCs) use a successive-approximation conversion
technique and input track/hold (T/H) circuitry to convert
an analog signal to a 10-bit digital output. A flexible
serial interface provides easy interface to microproces-
sors (µPs). Figure 3 is a block diagram of the
MAX1248/MAX1249.
The sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuit
(Figure 4). In single-ended mode, IN+ is internally
switched to CH0–CH3, and IN- is switched to COM. In
differential mode, IN+ and IN- are selected from two
pairs: CH0/CH1 and CH2/CH3. Configure the channels
with Tables 2 and 3. Please note that the codes for
CH0–CH3 in the MAX1248/MAX1249 correspond to
the codes for CH2–CH5 in the eight-channel
(MAX148/MAX149) versions.
In differential mode, IN- and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side (IN-) must remain sta-
ble within ±0.5LSB (±0.1LSB for best results) with
respect to AGND during a conversion. To accomplish
this, connect a 0.1µF capacitor from IN- (the selected
analog input) to AGND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C
acquisition interval spans three SCLK cycles and ends
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
Figure 3. Block Diagram
8
_______________Detailed Description
REFADJ
SHDN
SCLK
_______________________________________________________________________________________
COM
CH0
CH1
CH2
CH3
DIN
VREF
CS
15
16
14
9
8
7
2
3
4
5
6
*A 2.00 (MAX1249)
REGISTER
ANALOG
INPUT
SHIFT
INPUT
MUX
REFERENCE
(MAX1248)
+1.21V
CONTROL
LOGIC
Pseudo-Differential Input
T/H
20k
A 2.06*
+2.500V
IN
CLOCK
CLOCK
SAR
ADC
REF
INT
OUT
MAX1248
MAX1249
REGISTER
OUTPUT
SHIFT
HOLD
1
11
10
12
13
DOUT
SSTRB
V
DGND
AGND
DD
. The
on the falling SCLK edge after the last bit of the input
control word has been entered. At the end of the acqui-
sition interval, the T/H switch opens, retaining charge
on C
The conversion interval begins with the input multiplex-
er switching C
negative input (IN-). In single-ended mode, IN- is sim-
ply COM. This unbalances node ZERO at the compara-
tor’s input. The capacitive DAC adjusts during the
remainder of the conversion cycle to restore node
ZERO to 0V within the limits of 10-bit resolution. This
action is equivalent to transferring a charge of 16pF x
[(V
capacitive DAC, which in turn forms a digital represen-
tation of the analog input signal.
The T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. It enters its hold mode on the falling clock
edge after the eighth bit of the control word has been
shifted in. If the converter is set up for single-ended
inputs, IN- is connected to COM, and the converter
samples the “+” input. If the converter is set up for dif-
ferential inputs, IN- connects to the “-” input, and the
difference of
conversion, the positive input connects back to IN+,
and C
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
Figure 4. Equivalent Input Circuit
IN
SINGLE-ENDED MODE: IN+ = CHO–CH3, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
HOLD
+
COM
CH0
CH1
CH2
CH3
HOLD
) - (V
VREF
as a sample of the signal at IN+.
IN
charges to the input signal.
INPUT
|
-)] from C
MUX
IN+ - IN-
HOLD
C
CH0/CH1 AND CH2/CH3.
CAPACITIVE DAC
SWITCH
–
16pF
C
from the positive input (IN+) to the
HOLD
TRACK
SWITCH
|
+
HOLD
is sampled. At the end of the
T/H
R
9k
IN
HOLD
ZERO
to the binary-weighted
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
COMPARATOR
Track/Hold