MAX1248ACEE Maxim Integrated, MAX1248ACEE Datasheet - Page 7

• Manufacturer Part Number: MAX1248ACEE
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1248ACEE

• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 133 KSPs
• Resolution: 10 bit
• Input Type: Single-Ended/Differential
• Snr: 66 dB
• Interface Type: 4-Wire (SPI, Microwire, QSPI, TMS320)
• Operating Supply Voltage: 2.7 V to 5.25 V
• Maximum Operating Temperature: + 70 C
• Package / Case: QSOP-16
• Maximum Power Dissipation: 667 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Voltage Reference: 2.5 V

Figure 1. Load Circuits for Enable Time
______________________________________________________________Pin Description
DOUT
PIN
2–5
10
11
12
13
14
15
16
1
6
7
8
9
a) High-Z to V
6k
CH0–CH3
OH
REFADJ
DGND
SSTRB
NAME
DGND
SHDN
AGND
DOUT
SCLK
VREF
COM
V
and V
DIN
CS
DD
_______________________________________________________________________________________
OL
+2.7V to +5.25V, Low-Power, 4-Channel,
to V
OH
C
Positive Supply Voltage
Sampling Analog Inputs
Ground reference for analog inputs. Sets zero-code voltage in single-ended mode. Must be stable to
±0.5LSB.
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1248/MAX1249 down; otherwise, the
devices are fully operational. Pulling SHDN high puts the reference-buffer amplifier in internal compen-
sation mode. Letting SHDN float puts the reference-buffer amplifier in external compensation mode.
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion. In
internal reference mode (MAX1248 only), the reference buffer provides a 2.500V nominal output,
externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling
REFADJ to V
Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to V
Analog Ground
Digital Ground
Serial Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.
Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX1248/MAX1249 begin the
A/D conversion and goes high when the conversion is completed. In external clock mode, SSTRB
pulses high for one clock period before the MSB decision. High impedance when CS is high (external
clock mode).
Serial Data Input. Data is clocked in at SCLK’s rising edge.
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT is
high impedance.
Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed. (Duty cycle must be 40% to 60%.)
50pF
LOAD
b) High-Z to V
DOUT
DD
.
V
DD
OL
and V
Serial 10-Bit ADCs in QSOP-16
6k
C
DGND
50pF
LOAD
OH
to V
OL
Figure 2. Load Circuits for Disable Time
FUNCTION
DOUT
6k
a) V
OH
DGND
to High-Z
C
50pF
LOAD
DOUT
b) V
OL
V
DD
to High-Z
6k
C
DGND
50pF
LOAD
DD
.
7