S9S12G96F0MLH Freescale Semiconductor, S9S12G96F0MLH Datasheet - Page 645
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S9S12G96F0MLH
Manufacturer Part Number
S9S12G96F0MLH
Description
16-bit Microcontrollers - MCU 16BIT 96K FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G96F0MLH
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
96 KB
Data Ram Size
8192 B
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S9S12G96F0MLH
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Note: Bits related to available channels have functional significance. Writing to unavailable bits has no effect. Read from
19.3.2.6
The PWMCTL register provides for various control of the PWM module.
Read: Anytime
Write: Anytime
There are up to four control bits for concatenation, each of which is used to concatenate a pair of PWM
channels into one 16-bit channel. If the corresponding channels do not exist on a particular derivative, then
writes to these bits have no effect and reads will return zeroes. When channels 6 and 7are concatenated,
channel 6 registers become the high order bytes of the double byte channel. When channels 4 and 5 are
concatenated, channel 4 registers become the high order bytes of the double byte channel. When channels
2 and 3 are concatenated, channel 2 registers become the high order bytes of the double byte channel.
When channels 0 and 1 are concatenated, channel 0 registers become the high order bytes of the double
byte channel.
See
Function.
Freescale Semiconductor
Module Base + 0x0005
CAE[7:0]
Reset
Field
Section 19.4.2.7, “PWM 16-Bit Functions”
7–0
unavailable bits return a zero
W
R
CON67
Center Aligned Output Modes on Channels 7–0
0 Channels 7–0 operate in left aligned output mode.
1 Channels 7–0 operate in center aligned output mode.
PWM Control Register (PWMCTL)
0
7
Change these bits only when both corresponding channels are disabled.
CON45
= Unimplemented or Reserved
0
6
Figure 19-8. PWM Control Register (PWMCTL)
MC9S12G Family Reference Manual, Rev.1.23
Table 19-9. PWMCAE Field Descriptions
CON23
0
5
for a more detailed description of the concatenation PWM
CON01
NOTE
0
4
Description
PSWAI
0
3
Pulse-Width Modulator (S12PWM8B8CV2)
PFRZ
0
2
0
0
1
0
0
0
647
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