S9S12G96F0MLH Freescale Semiconductor, S9S12G96F0MLH Datasheet - Page 178
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S9S12G96F0MLH
Manufacturer Part Number
S9S12G96F0MLH
Description
16-bit Microcontrollers - MCU 16BIT 96K FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G96F0MLH
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
96 KB
Data Ram Size
8192 B
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S9S12G96F0MLH
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Port Integration Module (S12GPIMV1)
2.3.12
180
PJ1
PJ0
IBEx = ( (ATDDIENH/L[IENx]=1) OR (ATDCTL1[ETRIGSEL]=0 AND ATDCTL2[ETRIGE]=1) OR
Pins AD15-0
The following sources contribute to enable the input buffers on port AD:
•
•
•
•
Taking the availability of the different sources on each pin into account the
following logic equation must be true to activate the digital input buffer for
general-purpose input use:
• Except 20 TSSOP and 32 LQFP: The SPI1 MOSI signal is mapped to this pin when used with the SPI
• 48 LQFP: The TIM channel 6 signal is mapped to this pin when used with the timer function. The TIM
• Except 20 TSSOP and 32 LQFP: Pin interrupts can be generated if enabled in input or output mode.
• Signal priority:
• Except 20 TSSOP and 32 LQFP: The SPI1 MISO signal is mapped to this pin when used with the SPI
• 48 LQFP: The PWM channel 6 signal is mapped to this pin when used with the PWM function. The
• Except 20 TSSOP and 32 LQFP: Pin interrupts can be generated if enabled in input or output mode.
• Signal priority:
function. Depending on the configuration of the enabled SPI1 the I/O state is forced to be input or
output.
forces the I/O state to be an output for a timer port associated with an enabled output.
48 LQFP: MOSI1 > IOC6 > GPO
64/100 LQFP: MOSI1 > GPO
function. Depending on the configuration of the enabled SPI1 the I/O state is forced to be input or
output.
enabled PWM channel forces the I/O state to be an output.
48 LQFP: MISO1 > PWM6 > GPO
64/100 LQFP: MISO1 > GPO
Digital input enable register bits set for each individual pin in ADC
External trigger function of ADC enabled on ADC channel
ADC channels routed to port C freeing up pins
Digital input enable register set bit in and ACMP
(PRR1[PRR1AN]=1) ) AND (ACDIEN=1)
Table 2-15. Port
MC9S12G Family Reference Manual,
J
NOTE
Pins PJ7-0 (continued)
Rev.1.23
Freescale Semiconductor
Eqn. 2-1
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