MAX1075ETC-T Maxim Integrated, MAX1075ETC-T Datasheet - Page 13

• Manufacturer Part Number: MAX1075ETC-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1075ETC-T

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 1.8 MSPs
• Resolution: 10 bit
• Input Type: Differential
• Snr: No
• Interface Type: 3-Wire, Microwire, QSPI, Serial, SPI
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFN EP
• Maximum Power Dissipation: 1349 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: External

Unlike SPI, which requires two 1-byte reads to acquire
the 10 bits of data from the ADC, QSPI allows the mini-
mum number of clock cycles necessary to clock in the
data. The MAX1072/MAX1075 require 16 clock cycles
from the µP to clock out the 10 bits of data. Figure 14
shows a transfer using CPOL = 1 and CPHA = 1. The
conversion result contains three zeros, followed by the
10 data bits, 2 sub-bits, and a trailing zero with the data
in MSB-first format.
Figure 12. SPI/MICROWIRE Serial-Interface Timing—Single Conversion (CPOL = CPHA = 0), (CPOL = CPHA = 1)
Figure 13. SPI/MICROWIRE Serial-Interface Timing—Continuous Conversion (CPOL = CPHA = 0), (CPOL = CPHA = 1)
Figure 14. QSPI Serial-Interface Timing—Single Conversion (CPOL = 1, CPHA = 1)
CNVST
DOUT
SCLK
CNVST
DOUT
SCLK
HIGH-Z
CNVST
DOUT
SCLK
1
HIGH-Z
______________________________________________________________________________________
1
0
0
2
1.8Msps, Single-Supply, Low-Power,
0
D9
D9
D8
D9
D8
D8
True-Differential, 10-Bit ADCs
D7
D7
D7
QSPI
D6
D6
D6
8
D5
D5
D5
The MAX1072/MAX1075 can be directly connected
to the TMS320C54_ family of DSPs from Texas
Instruments, Inc. Set the DSP to generate its own
clocks or use external clock signals. Use either the
standard or buffered serial port. Figure 15 shows the
simplest interface between the MAX1072/MAX1075 and
the TMS320C54_, where the transmit serial clock
(CLKX) drives the receive serial clock (CLKR) and
SCLK, and the transmit frame sync (FSX) drives the
receive frame sync (FSR) and CNVST.
D4
9
D4
D4
D3
D3
D2
D3
DSP Interface to the TMS320C54_
D2
D1
D2
D0
D1
D1
S1
D0
D0
S0
14
16
S1
S1
HIGH-Z
S0
S0
16
16
0
HIGH-Z
1
0
13