MAX1075ETC-T Maxim Integrated, MAX1075ETC-T Datasheet - Page 11

• Manufacturer Part Number: MAX1075ETC-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1075ETC-T

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 1.8 MSPs
• Resolution: 10 bit
• Input Type: Differential
• Snr: No
• Interface Type: 3-Wire, Microwire, QSPI, Serial, SPI
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFN EP
• Maximum Power Dissipation: 1349 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: External

An external reference is required for the MAX1072/
MAX1075. Use a 4.7µF and 0.01µF bypass capacitor on
the REF pin for best performance. The reference input
structure allows a voltage range of +1V to V
An analog-to-digital conversion is initiated by CNVST,
clocked by SCLK, and the resulting data is clocked out
on DOUT by SCLK. With SCLK idling high or low, a
falling edge on CNVST begins a conversion. This causes
the analog input stage to transition from track to hold
mode, and DOUT to transition from high impedance to
being actively driven low. A total of 16 SCLK cycles are
required to complete a normal conversion. If CNVST is
low during the 16th falling SCLK edge, DOUT returns to
high impedance on the next rising edge of CNVST or
SCLK, enabling the serial interface to be shared by multi-
ple devices. If CNVST returns high after the 14th, but
before the 16th SCLK rising edge, DOUT remains active
so continuous conversions can be sustained. The high-
est throughput is achieved when performing continuous
conversions. Figure 10 illustrates a conversion using a
typical serial interface.
The MAX1072/MAX1075 serial interface is fully compati-
ble with SPI/QSPI and MICROWIRE (see Figure 11). If a
serial interface is available, set the CPU’s serial interface
in master mode so the CPU generates the serial clock.
Choose a clock frequency up to 28.8MHz.
When using SPI or MICROWIRE, the MAX1072/MAX1075
are compatible with all four modes programmed with the
CPHA and CPOL bits in the SPI or MICROWIRE control
register. Conversion begins with a CNVST falling edge.
DOUT goes low, indicating a conversion is in progress.
Two consecutive 1-byte reads are required to get the full
10 bits from the ADC. DOUT transitions on SCLK rising
edges. DOUT is guaranteed to be valid t
remains valid until t
edge. When using CPOL = 0 and CPHA = 0 or CPOL = 1
and CPHA = 1, the data is clocked into the µP on the
following rising edge. When using CPOL = 0 and CPHA
= 1 or CPOL = 1 and CPHA = 0, the data is clocked
into the µP on the next falling edge. See Figure 11 for
connections and Figures 12 and 13 for timing. See the
Timing Characteristics section to determine the best
mode to use.
Applications Information
______________________________________________________________________________________
DHOLD
How to Start a Conversion
Standard Interfaces
after the following SCLK rising
1.8Msps, Single-Supply, Low-Power,
SPI and MICROWIRE
External Reference
Connection to
DOUT
DD
.
True-Differential, 10-Bit ADCs
later and
Figure 8. Unipolar Transfer Function (MAX1072 Only)
Figure 9. Bipolar Transfer Function (MAX1075 Only)
111...111
111...110
111...101
000...011
000...010
000...001
000...000
011...111
011...110
000...010
000...001
000...000
111...111
111...110
111...101
100...001
100...000
OUTPUT CODE
OUTPUT CODE
0
FS
1
2
1 LSB =
- FS =
FS =
ZS = 0
3
V
1024
V
-V
REF
REF
2
REF
2
DIFFERENTIAL INPUT
DIFFERENTIAL INPUT
VOLTAGE (LSB)
VOLTAGE (LSB)
0
TRANSITION
FULL-SCALE
FULL-SCALE
TRANSITION
FS - 3/2 LSB
FS - 3/2 LSB
1 LSB =
FS = V
ZS = 0
FS
FS
V
1024
REF
REF
11