ispLSI 1048-80LQ Lattice, ispLSI 1048-80LQ Datasheet
ispLSI 1048-80LQ
Specifications of ispLSI 1048-80LQ
Related parts for ispLSI 1048-80LQ
ispLSI 1048-80LQ Summary of contents
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... The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status. Product Line Ordering Part Number ispLSI 1048-50LQ ispLSI 1048-70LQ ispLSI 1048 ispLSI 1048-80LQ ispLSI 1048-50LQI 5555 N.E. Moore Ct. Hillsboro, Oregon 97124-6421 Product Status Discontinued ...
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... The basic unit of logic on the ispLSI 1048 devices is the Generic Logic Block (GLB). The GLBs are labeled A0 (see figure 1). There are a total of 48 GLBs in the ispLSI 1048 device ...
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... IOCLK 0 and IOCLK 1) are provided to route clocks to the GLBs and I/O cells. The Clock Distribution Network can also be driven from a special clock GLB (D0 on the ispLSI 1048 device). The logic of this GLB allows the user to create an internal clock from a combination of internal signals within the device. ...
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... C, f=1.0 MHz) A SYMBOL PARAMETER C Dedicated Input Capacitance 1 C I/O and Clock Capacitance Guaranteed but not 100% tested. Data Retention Specifications PARAMETER Data Retention Erase/Reprogram Cycles Specifications ispLSI 1048 1 +1.0V CC +1.0V CC Commercial T = 0°C to +70°C A Industrial T = -40°C to +85° MAXIMUM 8 10 ...
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... Refer to the Power Consumption sec- CC tion of this datasheet and Thermal Management section of this Lattice Semiconductor Data Book or CD-ROM to estimate maximum Specifications ispLSI 1048 Figure 2. Test Load GND to 3.0V ≤ 3ns 10% to 90% 1.5V 1.5V ...
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... Refer to Timing Model in this data sheet for further details. 3. Standard 16-Bit loadable counter using GRP feedback. 4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. 5. Reference Switching Test Conditions section. Specifications ispLSI 1048 Over Recommended Operating Conditions 1 3 ...
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... ORP Bypass Delay 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. Specifications ispLSI 1048 -80 MIN. MAX. – – 5.3 1.5 – ...
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... Clock Delay, Clock GLB to I/O Cell Global Clock Line Global Reset Global Reset to GLB and I/O Registers 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. Specifications ispLSI 1048 1 7 -80 -70 -50 MIN. MAX. MIN. MAX. ...
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... Clock (max) + Reg co + Output ( gy0(max) + gco + ( ) ( = #50 + #40 + #52 + #40 21 (5.0 + 2.5 + 5.0) + (2.5) + (3.5 + 3.0) 1. Calculations are based upon timing specifications for the ispLSI 1048-70. Specifications ispLSI 1048 GRP GLB Feedback GRP Bypass GLB Reg Bypass #28 #33 GRP 20 PT Loading XOR Delays Delay #34, 35, 36 #27, 29, ...
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... Product Terms used. Fig- Figure 3. Typical Device Power Consumption vs fmax I CC can be estimated for the ispLSI 1048 using the following equation PTs * 0.23 nets * Max. freq * 0.010) where PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max ...
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... GND 46, 76,106 15, 45, 77, 107 1. Pins have dual function capability. Specifications ispLSI 1048 Input/Output Pins - These are the general purpose I/O pins used by the logic array Dedicated input pins to the device. (IN 2 and IN 9 not available) Input – Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode ...
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... Pin Configuration ispLSI 1048 120-Pin PQFP Pinout Diagram VCC 15 GND 16 1 ispEN 17 RESET 18 1 SDI ...
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... Family max (MHz) ispLSI 50 Specifications ispLSI 1048 — 1048 COMMERCIAL t Ordering Number pd (ns) 15 ispLSI 1048-80LQ ispLSI 1048-70LQ 18 ispLSI 1048-50LQ 24 INDUSTRIAL t Ordering Number pd (ns) 24 ispLSI 1048-50LQI 12 Grade Blank = Commercial I = Industrial Package Q = PQFP Power L = Low 0212-80B-isp1048 Package 120-Pin PQFP ...