ispLSI 1048-50LQI Lattice, ispLSI 1048-50LQI Datasheet - Page 11

• Manufacturer Part Number: ispLSI 1048-50LQI
• Description: CPLD - Complex Programmable Logic Devices USE ispMACH 4000V
• Manufacturer: Lattice

Specifications of ispLSI 1048-50LQI

• Memory Type: EEPROM
• Number Of Macrocells: 192
• Maximum Operating Frequency: 71.4 MHz
• Delay Time: 30.7 ns
• Number Of Programmable I/os: 96
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Package / Case: PQFP-120
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 120
• Supply Current: 260 mA
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V

Pin Description
1. Pins have dual function capability.
I/O 0 - I/O 5
I/O 6 - I/O 11
I/O 12 - I/O 17
I/O 18 - I/O 23
I/O 24 - I/O 29
I/O 30 - I/O 35
I/O 36 - I/O 41
I/O 42 - I/O 47
I/O 48 - I/O 53
I/O 54 - I/O 59
I/O 60 - I/O 65
I/O 66 - I/O 71
I/O 72 - I/O 77
I/O 78 - I/O 83
I/O 84 - I/O 89
I/O 90 - I/O 95
IN 4
IN 6 - IN 11
GND
V
ispEN
SDI/IN 0
MODE/IN 1
SDO/IN 3
SCLK/IN 5
RESET
Y0
Y1
Y2
Y3
CC
NAME
1
1
1
1
109,110,111,112,113,114,
115,116,117,118,119,120,
20, 21, 22, 23, 24, 25,
26, 27, 28, 29, 30, 31,
32, 33, 34, 35, 36, 37,
38, 39, 40, 41, 42, 43,
49, 50, 51, 52, 53, 54,
55, 56, 57, 58, 59, 60,
61, 62, 63, 64, 65, 66,
67, 68, 69, 70, 71, 72,
80, 81, 82, 83, 84, 85,
86, 87, 88, 89, 90, 91,
92, 93, 94, 95, 96, 97,
98, 99,100,101,102,103,
48,
79,104,105, – 108, 13
46, 76,106, 16
15, 45, 77, 107
PQFP PIN NUMBERS
17
19
44
47
73
18
14
78
75
74
1,
7,
2,
8,
3,
9, 10, 11, 12
4
5,
6,
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
Dedicated input pins to the device. (IN 2 and IN 9 not available)
Ground (GND)
V
Input – Dedicated in-system programming enable input pin. This pin
is brought low to enable the programming mode. The MODE, SDI,
SDO and SCLK options become active.
Input – This pin performs two functions. It is a dedicated input pin when
ispEN is logic high. When ispEN is logic low, it functions as an input
pin to load programming data into the device. SDI/IN 0 also is used as
one of the two control pins for the isp state machine.
Input – This pin performs two functions. It is a dedicated input pin when
ispEN is logic high. When ispEN is logic low, it functions as a pin to
control the operation of the isp state machine.
Input/Output – This pin performs two functions. It is a dedicated input
pin when ispEN is logic high. When ispEN is logic low, it functions as
an output pin to read serial shift register data.
Input – This pin performs two functions. It is a dedicated input when
ispEN is logic high. When ispEN is logic low, it functions as a clock pin
for the Serial Shift Register.
Active Low (0) Reset pin which resets all of the GLB and I/O registers
in the device.
Dedicated Clock input. This clock input is connected to one of the
clock inputs of all of the GLBs on the device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/or
any I/O cell on the device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on the
device.
CC
10
Specifications ispLSI 1048
DESCRIPTION
Table 2- 0002C-48-isp