ispLSI 1048-70LQ Lattice, ispLSI 1048-70LQ Datasheet - Page 2

• Manufacturer Part Number: ispLSI 1048-70LQ
• Description: CPLD - Complex Programmable Logic Devices USE ispMACH 4000V
• Manufacturer: Lattice

Specifications of ispLSI 1048-70LQ

• Memory Type: EEPROM
• Number Of Macrocells: 192
• Maximum Operating Frequency: 83 MHz
• Delay Time: 23 ns
• Number Of Programmable I/os: 96
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Package / Case: PQFP-120
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 120
• Supply Current: 235 mA
• Supply Voltage - Max: 5.25 V
• Supply Voltage - Min: 4.75 V

• HIGH-DENSITY PROGRAMMABLE LOGIC
• HIGH PERFORMANCE E
• IN-SYSTEM PROGRAMMABLE
• COMBINES EASE OF USE AND THE FAST SYSTEM
Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com
1048_07
Features
— 8000 PLD Gates
— 96 I/O Pins, Ten Dedicated Inputs
— 288 Registers
— High-Speed Global Interconnects
— Wide Input Gating for Fast Counters, State
— Small Logic Block Size for Random Logic
— Security Cell Prevents Unauthorized Copying
—
—
—
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile E
— 100% Tested
— In-System Programmable™ (ISP™) 5-Volt Only
— Increased Manufacturing Yields, Reduced Time-to-
— Reprogram Soldered Devices for Faster Debugging
SPEED OF PLDs WITH THE DENSITY AND FLEX-
— Complete Programmable Device Can Combine Glue
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
f
f
t
Market, and Improved Product Quality
Machines, Address Decoders, etc.
Logic and Structured Designs
Interconnectivity
max = 80 MHz Maximum Operating Frequency
max = 50 MHz for Industrial Devices
pd = 15 ns Propagation Delay
2
CMOS Technology
2
CMOS
®
TECHNOLOGY
1
In-System Programmable High Density PLD
The ispLSI 1048 is a High-Density Programmable Logic
Device which contain 288 Registers, 96 Universal I/O
pins, ten Dedicated Input pins, four Dedicated Clock
Input pins and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The ispLSI 1048 features 5-Volt in-system
programming and in-system diagnostic capabilities. It is
the first device which offers non-volatile reprogrammability
of the logic, as well as the interconnect to provide truly
reconfigurable systems.
The basic unit of logic on the ispLSI 1048 devices is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. F7 (see figure 1). There are a total of 48 GLBs in the
ispLSI 1048 device. Each GLB has 18 inputs, a program-
mable AND/OR/XOR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
other GLB on the device.
Functional Block Diagram
Description
A0
A1
A2
A3
A4
A5
A6
A7
F7 F6 F5 F4 F3 F2 F1 F0
B0 B1 B2 B3 B4 B5 B6 B7
Global Routing Pool (GRP)
Output Routing Pool
Output Routing Pool
ispLSI
E7 E6 E5 E4 E3 E2 E1 E0
C0 C1 C2 C3 C4 C5 C6 C7
Logic
Array
Output Routing Pool
Output Routing Pool
D Q
D Q
D Q
D Q
®
GLB
January 2002
1048
D7
D6
D5
D4
D3
D2
D1
D0
CLK