ADC1213D080HN-C1 IDT, ADC1213D080HN-C1 Datasheet - Page 21

• Manufacturer Part Number: ADC1213D080HN-C1
• Description: Analog to Digital Converters - ADC
• Manufacturer: IDT

Specifications of ADC1213D080HN-C1

• Rohs: yes

Integrated Device Technology
ADC1213D_SER 8
Product data sheet
Fig 21. General overview of the JESD204A serializer
S samples per frame cycle
N bits from Cr
CS bits for control
SYNC~
CS bits for control
N bits from Cr
M CONVERTERS
N' = N+CS
M−1
0
11.5.1 Digital JESD204A formatter
+
+
11.5 JESD204A serializer
Mx(N'xS) bits
lane stream mapping
For more information about the JESD204A standard refer to the JEDEC web site.
The block placed after the ADC cores is used to implement all functionalities of the
JESD204A standard. This ensures signal integrity and guarantees the clock and the data
recovery at the receiver side.
The block is highly parameterized and can be configured in various ways depending on
the sampling frequency and the number of lanes used.
samples stream to
TX transport layer
Fig 20. CML output connection to the receiver (AC-coupled)
HD: frame boundary break
CF: position of control bits
Padding with Tail bits (TT)
L LANES
F octets
F octets
+
Lx(F) octets
Rev. 08 — 2 July 2012
OCTETS
OCTETS
FRAME
FRAME
VDDD
TO
TO
12 mA to 26 mA
L octets
50 Ω
−
SCRAMBLER
SCRAMBLER
CMLPA/CMLPB
CMLNA/CMLNB
Dual 12-bit ADC; serial JESD204A interface
10 nF
10 nF
TX CONTROLLER
CHARACTER
GENERATOR
CHARACTER
GENERATOR
ALIGNMENT
ALIGNMENT
ADC1213D series
100 Ω
10-bit
10-bit
8-bit/
8-bit/
RECEIVER
005aaa083
005aaa084
SER
SER
© IDT 2012. All rights reserved.
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