ADC1213D080HN-C1 IDT, ADC1213D080HN-C1 Datasheet - Page 14

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ADC1213D080HN-C1

Manufacturer Part Number
ADC1213D080HN-C1
Description
Analog to Digital Converters - ADC
Manufacturer
IDT
Datasheet

Specifications of ADC1213D080HN-C1

Rohs
yes
Integrated Device Technology
ADC1213D_SER 8
Product data sheet
11.1.2 Anti-kickback circuitry
The sample phase occurs when the internal clock (derived from the clock signal on pin
CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the
clock signal goes LOW, the stage enters the hold phase and the voltage information is
transmitted to the ADC core.
Anti-kickback circuitry (RC filter in Figure 7) is needed to counteract the effects of a
charge injection generated by the sampling capacitance.
The RC filter is also used to filter noise from the signal before it reaches the sampling
stage. The value of the capacitor should be chosen to maximize noise attenuation without
degrading the settling time excessively.
The component values are determined by the input frequency and should be selected so
as not to affect the input bandwidth.
Fig 6.
Fig 7.
Input sampling circuit
Anti-kickback circuit
INAM
INBM
INAP
INBP
1, 14
2, 13
Rev. 08 — 2 July 2012
package
ESD
R
R
Dual 12-bit ADC; serial JESD204A interface
parasitics
C
001aan679
INAM/
INAP/
INBM
INBP
ADC1213D series
R on = 15 Ω
R on = 15 Ω
internal
internal
switch
switch
clock
clock
4 pF
4 pF
C s
C s
005aaa069
© IDT 2012. All rights reserved.
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