ispLSI 2096A-125LT128 Lattice, ispLSI 2096A-125LT128 Datasheet - Page 6
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ispLSI 2096A-125LT128
Manufacturer Part Number
ispLSI 2096A-125LT128
Description
CPLD - Complex Programmable Logic Devices USE ispMACH 4000V
Manufacturer
Lattice
Datasheet
1.ISPLSI_2096A-100LT128.pdf
(12 pages)
Specifications of ispLSI 2096A-125LT128
Memory Type
EEPROM
Number Of Macrocells
96
Maximum Operating Frequency
125 MHz
Delay Time
10 ns
Number Of Programmable I/os
96
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Package / Case
TQFP-128
Mounting Style
SMD/SMT
Factory Pack Quantity
450
Supply Current
295 mA
Supply Voltage - Max
5.25 V
Supply Voltage - Min
4.75 V
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
PARAMETER
Internal Timing Parameters
Inputs
t
t
GRP
t
GLB
t
t
t
t
t
t
t
t
t
t
t
t
t
ORP
t
t
Outputs
t
t
t
t
t
Clocks
t
t
Global Reset
t
io
din
grp
4ptbpc
4ptbpr
1ptxor
20ptxor
xoradj
gbp
gsu
gh
gco
gro
ptre
ptoe
ptck
orp
orpbp
ob
sl
oen
odis
goe
gy0
gy1/2
gr
20 Input Buffer Delay
21 Dedicated Input Delay
22 GRP Delay
23 4 Product Term Bypass Comb. Path Delay
24
25
26
27
28
29
30
31
32
33
34
35 GLB Product Term Clock Delay
36 ORP Delay
37 ORP Bypass Delay
38 Output Buffer Delay
39 Output Slew Limited Delay Adder
40 I/O Cell OE to Output Enabled
41 I/O Cell OE to Output Disabled
42 Global Output Enable
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. Clock)
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
45 Global Reset to GLB
#
2
4 Product Term Bypass Reg. Path Delay
1 Product Term/XOR Path Delay
20 Product Term/XOR Path Delay
XOR Adjacent Path Delay
GLB Register Bypass Delay
GLB Register Setup Time before Clock
GLB Register Hold Time after Clock
GLB Register Clock to Output Delay
GLB Register Reset to Output Delay
GLB Product Term Reset to Register Delay
GLB Product Term Output Enable to I/O Cell Delay
Over Recommended Operating Conditions
1
DESCRIPTION
3
6
Specifications ispLSI 2096/A
MIN. MAX.
0.8
3.0
3.3
2.3
2.3
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
-125
10.0
0.8
0.3
1.2
3.2
3.2
3.8
2.3
2.3
6.9
0.2
1.5
4.5
5.0
5.7
6.0
6.5
0.5
0.2
1.1
4.8
7.3
1.3
5.6
–
–
MIN.
1.2
4.0
4.1
2.7
2.7
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
-100
MAX.
10.0
1.4
0.4
1.6
4.2
4.2
4.8
2.7
2.7
9.2
0.5
2.2
5.8
5.8
6.8
7.3
8.0
0.5
0.3
1.3
6.1
8.6
1.7
7.1
–
–
MIN.
1.4
6.0
5.6
3.6
3.6
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
-80
MAX.
10.2
10.0
11.4
1.8
4.4
2.6
8.1
6.8
8.0
8.8
9.8
1.3
0.4
1.6
8.6
9.0
2.0
0.5
2.0
4.6
4.6
7.4
3.6
3.6
–
–
Table 2-0036/2096
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns