dsPIC33FJ32GP104-I/PT Microchip Technology, dsPIC33FJ32GP104-I/PT Datasheet - Page 227

• Manufacturer Part Number: dsPIC33FJ32GP104-I/PT
• Description: Digital Signal Processors & Controllers - DSP, DSC 16bit Gen Prp Fam16 MIPS 32KBFLSH 2KBRAM
• Manufacturer: Microchip Technology
• Type: dsPIC33FJ32(GP/MC)101/102/104r

Specifications of dsPIC33FJ32GP104-I/PT

• Rohs: yes
• Core: dsPIC33F
• Data Bus Width: 16 bit
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 16 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33FJ32(GP/MC)101/102/104
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

REGISTER 19-7:
 2011-2012 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14-13
bit 12-0
Note 1:
PCFG15
PCFG7
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
R/W-0
R/W-0
2:
3:
4:
5:
6:
7:
(4,5)
(4,5)
On devices without 14 analog inputs, all PCFG bits are R/W by user. However, PCFGx bits are ignored on
ports without a corresponding input on the device.
PCFGx = ANx, where x = 0 through 12, and 15.
The PCFGx bits have no effect if the ADC module is disabled by setting the AD1MD bit in the PMD1 register.
When the bit is set, all port pins that have been multiplexed with ANx will be in Digital mode.
Pins shared with analog functions (i.e., ANx) are analog by default and therefore, must be set by the user
to enable any digital function on that pin. Reading any port pin with the analog function enabled will return
a ‘0’, regardless of the signal input level.
The PCFG<15,12:11,8:6> bits are available in the dsPIC33FJ32(GP/MC)104 devices only and are
reserved in all other devices.
The PCFG<5:4> bits are available on all devices, excluding the dsPIC33FJXX(GP/MC)101 devices, where
they are reserved.
The PCFG<10:9> bits are available on all devices, excluding the dsPIC33FJ16(GP/MC)101/102 devices,
where they are reserved.
PCFG15: ADC Port Configuration Control bit
1 = Port pin is in Digital mode, port read input is enabled, ADC input multiplexer is connected to AV
0 = Port pin is in Analog mode, port read input is disabled, ADC samples pin voltage
Unimplemented: Read as ‘0’
PCFG<12:0>: ADC Port Configuration Control bits
1 = Port pin is in Digital mode, port read input is enabled, ADC input multiplexer is connected to AV
0 = Port pin is in Analog mode, port read input is disabled, ADC samples pin voltage
PCFG6
R/W-0
U-0
—
AD1PCFGL: ADC1 PORT CONFIGURATION REGISTER LOW
(4,5)
W = Writable bit
‘1’ = Bit is set
PCFG5
R/W-0
U-0
—
(4,6)
PCFG12
PCFG4
R/W-0
R/W-0
(4,6)
(4,5)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PCFG11
(4,5)
PCFG3
R/W-0
R/W-0
(4,5,6,7)
(4,5)
(4)
PCFG10
PCFG2
R/W-0
R/W-0
(4,7)
(4)
x = Bit is unknown
PCFG9
PCFG1
R/W-0
R/W-0
(1,2,3)
(4,7)
DS70652E-page 227
(4)
PCFG8
PCFG0
R/W-0
R/W-0
(4,5)
bit 8
bit 0
(4)
SS
SS