MAX1464CAI+T Maxim Integrated, MAX1464CAI+T Datasheet - Page 31

• Manufacturer Part Number: MAX1464CAI+T
• Description: Digital Signal Processors & Controllers - DSP, DSC Low-Power Low-Noise Multichannel Sensor Signal Processor
• Manufacturer: Maxim Integrated
• Series: MAX1464r

Specifications of MAX1464CAI+T

• Data Bus Width: 16 bit
• Program Memory Size: 4 KB, 128 B
• Maximum Clock Frequency: 5.3 MHz
• Number Of Programmable I/os: 2
• Operating Supply Voltage: 5 V
• Interface Type: SPI
• On-chip Adc: Yes
• Processor Series: MAX1464
• Product: DSPs
• Program Memory Type: Flash

Table 10. ADC_Config_2A (Address = 05h)
Table 7. Single-Ended (SE[3:0])
*The PGA operates at a fixed reduced gain of 0.7V/V to enable conversion of input signals at and near V
ting is not selectable.
**When measuring V
Table 8. ADC_Config_1A (Address = 02h)
Table 9. ADC_Config_1B (Address = 03h)
15–11
15–11
10–8
15–7
10–8
SE[3:0]
BIT
6–4
2–0
BIT
6–4
3–2
1–0
BIT
2–0
0001
0010
0011
0100
0101
0110
0111
1000
1001
7
3
7
6
3
BIAS1[2:0]
PGA1[4:0]
PGA2[4:0]
CLK2[2:0]
CLK1[2:0]
RES1[2:0]
REF1[1:0]
RES2[2:0]
CO1[2:0]
CO2[2:0]
CO1[3]
CO2[3]
NAME
NAME
NAME
RANGE (V/V)
0.99 to 244
0.99 to 244
0.99 to 244
0.99 to 244
DD
—
—
—
—
______________________________________________________________________________________
, use the external reference or the 4 x V
PGA
0.99
0.7*
0.7*
0.7*
0.7*
Programmable-gain amplifier setting to use during conversion of channel 1. PGA1[4] = MSB.
ADC clock setting to use during conversion of channel 1. CLK1[2] = MSB.
Unused.
ADC resolution setting to use during conversion of channel 1. RES1[2] = MSB.
Coarse-offset sign bit.
Coarse-offset DAC setting to use during conversion of channel 1. CO1[2] = MSB.
Unused.
ADC bias setting to use during conversion of channel 1. BIAS1[2] = MSB.
Unused.
Reference select for conversion on channel 1. REF1[1] = MSB.
Programmable-gain amplifier to use during conversion of channel 2. PGA[4] = MSB.
ADC clock setting to use during conversion of channel 2. CLK2[2] = MSB.
Unused.
ADC resolution setting to use during conversion of channel 2. RES2[2] = MSB.
Coarse-offset DAC sign bit.
Coarse-offset DAC setting to use during conversion of channel 2. CO2[2] = MSB.
Low-Power, Low-Noise Multichannel
DACn_OUT using
DACn_OUT using
OUTnSM
OUTnLG
OUTnSM
OUTnLG
+INPUT
V
INMn
ADC
VBG
INPn
V
DD
SS
**
BG
Sensor Signal Processor
-INPUT
setting.
ADC
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
DESCRIPTION
DESCRIPTION
DESCRIPTION
Bandgap voltage.
Output of small op-amp n.
Output of large op-amp n.
Power-supply voltage.
Power-supply ground.
DACn output through small op-amp n configured
as unity-gain buffer.
DACn output through large op-amp n configured
as unity-gain buffer.
Single-ended input on INPn.
Single-ended input on INMn.
DESCRIPTION
DD
and V
SS
. This gain set-
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