SSTV16857ATE-E Renesas Electronics America, SSTV16857ATE-E Datasheet - Page 7

• Manufacturer Part Number: SSTV16857ATE-E
• Description: IC REGISTER DRVR 14BIT
• Manufacturer: Renesas Electronics America
• Series: 74SSTVr

Specifications of SSTV16857ATE-E

• Logic Type: 1:1 14-Bit SSTL_2 Registered Buffer
• Supply Voltage: 2.3 V ~ 2.7 V
• Number Of Bits: 14
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

HD74SSTV16857A
Switching Characteristics
Clock frequency
Setup time
Hold time
Differential inputs active time
Differential inputs inactive time
Pulse width Output slew
Maximum clock frequency
Propagation delay time
Notes: 1. Although the clock is differential, all timing is relative to CLK going high and CLK going low.
Rev.1.00 Apr 07, 2006 page 5 of 10
2. This timing relationship is specified into test load (see waveforms – 3, 4) with all of the outputs switching.
3. Assumes into an equivalent, distributed load to the address net structure defined in the application
4. For data signal input slew rate
5. For data signal input slew rate
6. CLK, CLK signals input slew rates are
information provided in this specification.
Item
*1
Item
Fast slew rate
Slow slew rate
Fast slew rate
Slow slew rate
*2
*3
Symbol
*4, 6
*4, 6
t
*5, 6
*5, 6
PLH,
f
t
max
PHL
t
PHL
Symbol
f
t
clock
1 V/ns.
0.5 V/ns and < 1 V/ns.
t
inact
t
t
t
t
act
SL
su
w
h
Min
200
1.1
—
1 V/ns.
V
CC
V
0.75
0.75
Min
0.9
0.9
2.5
= 2.5±0.2 V
22
22
—
CC
1
Typ
—
—
—
= 2.5 ± 0.2 V
Max
200
Max
—
—
—
—
—
—
—
2.8
5.0
(C
—
4
L
= 30 pF, R
volt/ns
MHz
Unit
MHz
Unit
ns
ns
ns
ns
ns
ns
L
= 50 , V
CLK CLK “H” or “L”
CLK, CLK
RESET
Data before CLK , CLK
Data after CLK , CLK
Data inputs must be low after
RESET high.
Data and clock inputs must
be held at valid levels (not
floating) after RESET low.
(Input)
FROM
REF
Test Condition
= V
TT
Q
Q
= V
(Output)
DDQ
TO
0.5)