IS45S16400F-6TLA2 ISSI, IS45S16400F-6TLA2 Datasheet - Page 12

• Manufacturer Part Number: IS45S16400F-6TLA2
• Description: DRAM 64M (4Mx16) 166MHz Automotive Temp
• Manufacturer: ISSI

Specifications of IS45S16400F-6TLA2

• Product Category: DRAM
• Rohs: yes
• Data Bus Width: 16 bit
• Package / Case: TSOP-54
• Memory Size: 64 Mbit
• Maximum Clock Frequency: 166 MHz
• Access Time: 6 ns, 5.4 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V
• Maximum Operating Current: 140 mA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 108

IS42S16400F
IS45S16400F
8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the AUTO PRECHARGE command when its burst has been inter-
9. Burst in bank n continues as initiated.
10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt
11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will inter-
12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will inter-
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt
12
rupted by bank m’s burst.
the READ on bank n, CAS latency later (Consecutive READ Bursts).
rupt the READ on bank n when registered (READ to WRITE). DQM should be used one clock prior to the WRITE command to
prevent bus contention.
the WRITE on bank n when registered (WRITE to READ), with the data-out appearing CAS latency later. The last valid WRITE
to bank n will be data-in registered one clock prior to the READ to bank m.
rupt the WRITE on bank n when registered (WRITE to WRITE). The last valid WRITE to bank n will be data-in registered one
clock prior to the READ to bank m.
READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Fig CAP
1).
the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention.
The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Fig CAP 2).
the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will begin
after t
tered one clock prior to the READ to bank m (Fig CAP 3).
the WRITE on bank n when registered. The PRECHARGE to bank n will begin after t
WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to bank m
(Fig CAP 4).
WR
is met, where t
wr
begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in regis-
Integrated Silicon Solution, Inc. — www.issi.com
wr
is met, where t WR begins when the
12/01/2011
Rev. I