N74F786D,623 NXP Semiconductors, N74F786D,623 Datasheet - Page 2
![IC ARBITER BUS 5.5V 16SOIC](/photos/6/52/65286/16-soic_sot109-1_sml.jpg)
N74F786D,623
Manufacturer Part Number
N74F786D,623
Description
IC ARBITER BUS 5.5V 16SOIC
Manufacturer
NXP Semiconductors
Series
74Fr
Datasheet
1.N74F786D602.pdf
(12 pages)
Specifications of N74F786D,623
Logic Type
Bus Arbiter
Supply Voltage
4.5 V ~ 5.5 V
Number Of Bits
4
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
16-SOIC (3.9mm Width)
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Package Type
SO
Pin Count
16
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
933906250623
N74F786D-T
N74F786D-T
N74F786D-T
N74F786D-T
Philips Semiconductors
FEATURES
DESCRIPTION
The 74F786 is an asynchronous 4–bit arbiter designed for high
speed real–time applications. The priority of arbitration is determined
on a first–come first–served basis. Separate bus grant (BGn)
outputs are available to indicate which one of the request inputs is
served by the arbitration logic. All BGn outputs are enabled by a
common enable (EN) pin. In order to generate a bus request signal
a separate 4 input AND gate is provided which may also be used as
an independent AND gate. Unused bus request (BR) inputs may be
disabled by tying them high.
ORDERING INFORMATION
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
NOTE:
One (1.0) FAST unit load is defined as: 20 A in the high state and 0.6mA in the low state.
LOGIC SYMBOL
February 14, 1991
Arbitrates between 4 asynchronous inputs
Separate grant output for each input
Common output enable
On board 4 input AND gate
Metastable–free outputs
Industrial temperature range available (–40 C to +85 C)
V
GND = Pin 8
4-bit asynchronous bus arbiter
16–pin plastic DIP
16–pin plastic SO
CC
DESCRIPTION
= Pin 16
BG0 – BG3
BR0 – BR3
A, B, C, D
YOUT
PINS
EN
6
BR0 BR1 BR2 BR3
EN
4
BG0 BG1 BG2 BG3 YOUT
5
13
6
Bus request inputs (active low)
AND gate inputs
Common bus grant output enable input (active low)
AND gate output
Bus grant outputs (active low)
12
COMMERCIAL RANGE
T
7
amb
V
11
CC
15
A
N74F786N
N74F786D
= 0 C to +70 C
= 5V 10%,
10
1
B
SF00442
14
2
C
D
3
DESCRIPTION
ORDER CODE
2
The 74F786 is designed so that contention between two or more
request signals will not glitch or display a metastable condition. In
this situation an increase in the BRn to BGn t
A typical 74F786 has an h = 6.6ns, t = 0.41ns and To = 5 sec.
Where:
h = Typical propagation delay through the device and t and To are
device parameters derived from test results and can most nearly be
defined as:
t = A function of the rate at which a latch in a metastable state
resolves that condition.
To = A function of the measurement of the propensity of a latch to
enter a metastable state. To is also a very strong function of the
normal propagation delay of the device.
For further information, please refer to the 74F786 application notes.
IEC/IEEE SYMBOL
74F786
T
INDUSTRIAL RANGE
TYPE
amb
V
CC
= –40 C to +85 C
I74F786N
I74F786D
= 5V 10%,
PROPAGATION DELAY
15
1
2
3
9
4
5
6
7
74F (U.L.) HIGH/
TYPICAL
6.6ns
EN
BR0
BR1
BR2
BR3
1.0/3.0
1.0/1.0
1.0/1.0
150/40
150/40
LOW
BUS ARBITER
74F786
&
BG0
BG1
BG2
BG3
PHL
LOAD VALUE HIGH/
SF00443
SUPPLY CURRENT
Product specification
14
13
12
11
10
PKG DWG #
may be observed.
3.0mA/24mA
3.0mA/24mA
20 A/1.8mA
20 A/0.6mA
20 A/0.6mA
853–1269 01717
SOT109-1
SOT 38-4
TYPICAL
(TOTAL)
74F786
55mA
LOW