GTL1655DGG,518 NXP Semiconductors, GTL1655DGG,518 Datasheet - Page 2

• Manufacturer Part Number: GTL1655DGG,518
• Description: IC TXRX BUS 16BIT 3-3.6V TSSOP64
• Manufacturer: NXP Semiconductors

Specifications of GTL1655DGG,518

• Logic Function: *
• Number Of Bits: 16
• Input Type: *
• Output Type: *
• Data Rate: *
• Number Of Channels: *
• Number Of Outputs/channel: *
• Differential - Input:output: *
• Propagation Delay (max): *
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TSSOP
• Mounting Type: Surface Mount
• Supply Voltage: 3 V ~ 3.6 V
• Logic Type: LVTTL-TO-GTL/GTL+ TRANSCEIVER
• Logic Family: GTL
• Operating Supply Voltage (typ): 3.3V
• Propagation Delay Time: 7.2ns
• Number Of Elements: 1
• Input Logic Level: LVTTL/TTL
• Output Logic Level: GTL
• Package Type: TSSOP
• Polarity: Non-Inverting
• Logical Function: Universal Bus Transceiver
• Operating Supply Voltage (min): 3V
• Technology: BiCMOS
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935270638518; GTL1655DGG-T; GTL1655DGG-T

Philips Semiconductors
2. Features
3. Quick reference data
Table 1:
GND = 0 V; T
9397 750 12936
Product data
Symbol
t
t
C
C
PLH
PHL
i
I/O
Quick reference data
Parameter
propagation delay, nAn to nBn
propagation delay, nBn to nAn
propagation delay, nAn to nBn
propagation delay, nBn to nAn
input capacitance (control pins)
I/O capacitance, Port A
I/O capacitance, Port B
amb
= 25 C; t
r
= t
f
2.5 ns
Combination of D-type latches and D-type flip-flops for transceiver operation in
clocked, latched or transparent mode
Logic level translation between LVTTL and GTL/GTL+ signals
HIGH-drive LOW-output-impedance (100 mA/12 ) on Port B
Configurable rise and fall times on Port B
Supports live insertion (I
Bus Hold on Port A inputs
Over voltage tolerance on Port A
Minimized switching noise through use of distributed V
Available in TSSOP64 package
Industrial temperature range ( 40 C to +85 C)
ESD protection
Latch-up EIA/JEDS78 exceeds 200 mA
HBM EIA/JESD22-A114-A exceeds 2000 V
CDM EIA/JESD22-C101 exceeds 1000 V
Rev. 01 — 11 May 2004
Conditions
V
V
V
V
V
V
V
V
V
V
V
V
V
16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
CC
TT
CC
TT
CC
CC
TT
CC
TT
CC
i
i
i
= V
= V
= V
= 1.5 V; V
= 1.5 V; V
= 1.5 V; V
= 1.5 V; V
= 3.3 V; V
= 3.3 V; V
= 3.3 V
= 3.3 V; V
= 3.3 V; V
= 3.3 V
CC
CC
CC
or GND
or GND
or GND
off
, Power-up 3-state, and BIAS V
REF
REF
REF
REF
ERC
ERC
ERC
ERC
= 1 V
= 1 V
= 1 V
= 1 V
= GND;
= GND;
= GND;
= GND;
Min
-
-
-
-
-
-
-
-
-
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Typ
3.9
4.4
2.6
3.1
2.7
4.2
3
7
8
CC
and GND pins
CC
)
GTL1655
Max
-
-
-
-
-
-
-
-
-
Unit
ns
ns
ns
ns
ns
ns
pF
pF
pF
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