SSTUA32864EC,557 NXP Semiconductors, SSTUA32864EC,557 Datasheet - Page 6

• Manufacturer Part Number: SSTUA32864EC,557
• Description: IC BUFFER 1.8V 25BIT SOT536
• Manufacturer: NXP Semiconductors

Specifications of SSTUA32864EC,557

• Logic Type: 1:1, 1:2 Configurable Registered Buffer
• Supply Voltage: 1.7 V ~ 2 V
• Number Of Bits: 25, 14
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 96-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935279439557; SSTUA32864EC; SSTUA32864EC

NXP Semiconductors
Table 2.
[1]
[2]
[3]
SSTUA32864_2
Product data sheet
Symbol
GND
V
VREF
ZOH
ZOL
CK
CK
C0, C1
RESET
CSR, DCS
D1 to D25
DODT
DCKE
Q1 to Q25,
Q1A to Q14A,
Q1B to Q14B
QCS, QCSA,
QCSB
QODT, QODTA,
QODTB
QCKE, QCKEA,
QCKEB
n.c.
DNU
DD
Depends on configuration. See
Configurations:
Data inputs = D2, D3, D5, D6, D8 to D25 when C0 = 0 and C1 = 0.
Data inputs = D2, D3, D5, D6, D8 to D14 when C0 = 0 and C1 = 1.
Data inputs = D1 to D6, D8 to D10, D12, D13 when C0 = 1 and C1 = 1.
Configurations:
Data outputs = Q2, Q3, Q5, Q6, Q8 to Q25 when C0 = 0 and C1 = 0.
Data outputs = Q2, Q3, Q5, Q6, Q8 to Q14 when C0 = 0 and C1 = 1.
Data outputs = Q1 to Q6, Q8 to Q10, Q12, Q13 when C0 = 1 and C1 = 1.
Pin description
6.2 Pin description
Pin
B3, B4, D3, D4, F3, F4,
H3, H4, K3, K4, M3,
M4, P3, P4
A4, C3, C4, E3, E4,
G3, G4, J3, J4, L3, L4,
N3, N4, R3, R4, T4
A3, T3
J5
J6
H1
J1
G6, G5
G2
J2, H2
[1]
[1]
[1]
[1]
[1]
[1]
[1]
A2, D2, G1
[1]
Figure
3,
1.8 V configurable registered buffer for DDR2-667 RDIMM applications
Figure
Type
ground input
1.8 V nominal
0.9 V nominal
input
input
differential input positive master clock input
differential input negative master clock input
LVCMOS inputs configuration control inputs
LVCMOS input
SSTL_18 input
SSTL_18 input
SSTL_18 input
SSTL_18 input
1.8 V CMOS
1.8 V CMOS
1.8 V CMOS
1.8 V CMOS
-
-
4, and
Rev. 02 — 9 March 2007
Figure 5
for ball number.
Description
ground
power supply voltage
input reference voltage
reserved for future use
reserved for future use
Asynchronous reset input (active LOW). Resets registers and
disables VREF data and clock differential-input receivers.
Chip select inputs (active LOW). Disables data outputs
switching when both inputs are HIGH.
Data inputs. Clocked in on the crossing of the rising edge of
CK and the falling edge of CK.
The outputs of this register will not be suspended by DCS and
CSR control.
The outputs of this register will not be suspended by DCS and
CSR control.
The outputs that are suspended by DCS and CSR control
Data outputs that will not be suspended by DCS and CSR
control.
Data outputs that will not be suspended by DCS and CSR
control.
Data outputs that will not be suspended by DCS and CSR
control.
Not connected. Ball present but no internal connection to the
die.
Do-not-use. Ball internally connected to the die which should
be left open-circuit.
SSTUA32864
[2]
© NXP B.V. 2007. All rights reserved.
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[3]
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