SSTUH32866EC/G,557 NXP Semiconductors, SSTUH32866EC/G,557 Datasheet - Page 16

• Manufacturer Part Number: SSTUH32866EC/G,557
• Description: IC BUFFER 1.8V 25BIT SOT536-1
• Manufacturer: NXP Semiconductors

Specifications of SSTUH32866EC/G,557

• Logic Type: 1:1, 1:2 Configurable Registered Buffer with Parity
• Supply Voltage: 1.7 V ~ 1.9 V
• Number Of Bits: 25, 14
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 96-LFBGA
• Logic Family: SSTU
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Inputs: 25
• Number Of Outputs: 25
• High Level Output Current: -12mA
• Low Level Output Current: 12mA
• Package Type: LFBGA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 450(Min)MHz
• Mounting: Surface Mount
• Pin Count: 96
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935277966557; SSTUH32866EC/G; SSTUH32866EC/G

Philips Semiconductors
9397 750 14199
Product data sheet
Fig 9. Timing diagram for the second SSTUH32866 (1 : 2 Register B configuration) device used in pair;
(not used)
PAR_IN
RESET
QERR
(1) PAR_IN is driven from PPO of the first SSTUH32866 device.
DCS
CSR
PPO
Q14
D14
CK
CK
Q1
D1
to
to
(1)
C0 = 1, C1 = 1
CK to Q
t
PD
t
su
m
t
h
1.8 V high-drive DDR2 configurable registered buffer with parity
Rev. 01 — 13 May 2005
m + 1
CK to QERR
CK to PPO
t
t
PD
PD
t
su
m + 2
t
h
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
m + 3
SSTUH32866
CK to QERR
t
PD
m + 4
002aaa657
16 of 28