SSTV16857DGG,518 NXP Semiconductors, SSTV16857DGG,518 Datasheet - Page 2

• Manufacturer Part Number: SSTV16857DGG,518
• Description: IC REG DRIVER 14BIT 48TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74SSTVr

Specifications of SSTV16857DGG,518

• Logic Type: SSTL_2 Registered Driver with Differential Clock Inputs
• Supply Voltage: 2.3 V ~ 2.7 V
• Number Of Bits: 14
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935268661518; SSTV16857DGG-T; SSTV16857DGG-T

The SSTV16857 is a 14-bit SSTL_2 registered driver with differential
Philips Semiconductors
FEATURES
DESCRIPTION
clock inputs, designed to operate between 2.3 V and 2.7 V. V
must not exceed V
0.5*V
standard stub-series applications or capacitive loads. Master reset
(RESET) asynchronously resets all registers to zero.
The SSTV16857 is intended to be incorporated into standard DIMM
(Dual In-Line Memory Module) designs defined by JEDEC, such as
DDR (Double Data Rate) SDRAM or SDRAM II Memory Modules.
Different from traditional SDRAM, DDR SDRAM transfers data on
both clock edges (rising and falling), thus doubling the peak bus
bandwidth. A DDR DRAM rated at 133 MHz will have a burst rate of
266 MHz. The modules require between 23 and 27 registered
control and address lines, so two 14-bit wide devices will be used on
each module. The SSTV16857 is intended to be used for SSTL_2
input and output signals.
The device data inputs consist of differential receivers. One
differential input is tied to the input pin while the other is tied to a
reference input pad, which is shared by all inputs.
The clock input is fully differential to be compatible with DRAM
devices that are installed on the DIMM. However, since the control
inputs to the SDRAM change at only half the data rate, the device
must only change state on the positive transition of the CLK signal.
In order to be able to provide defined outputs from the device even
before a stable clock has been supplied, the device must support an
asynchronous input pin (reset), which when held to the LOW state
will assume that all registers are reset to the LOW state and all
outputs drive a LOW signal as well.
QUICK REFERENCE DATA
GND = 0 V; T
ORDERING INFORMATION
48-Pin Plastic TSSOP
48-Pin Plastic TSSOP (TVSOP)
56-Ball Plastic VFBGA
2002 Sep 27
Stub-series terminated logic for 2.5 V V
Optimized for DDR (Double Data Rate) SDRAM applications
Inputs compatible with JESD8–9 SSTL_2 specifications.
Flow-through architecture optimizes PCB layout
ESD classification testing is done to JEDEC Standard JESD22.
Protection exceeds 2000 V to HBM per method A114.
Latch-up testing is done to JEDEC Standard JESD78, which
exceeds 100 mA.
Same form, fit, and function as SSTL16877
Full DDR 200/266 solution @ 2.5 V when used with PCKV857
See SSTV16856 for driver/buffer version with mode select.
Available in TSSOP-48, TVSOP-48 and 56 ball VFBGA packages
14-bit SSTL_2 registered driver
with differential clock inputs
DDQ
SYMBOL
t
PHL
. The outputs support class I which can be used for
C
/t
I
amb
PLH
PACKAGES
= 25 C; t
CC
. Inputs are SSTL_2 type with V
Propagation delay; CLK to Qn
Input capacitance
r
=t
f
2.5 ns
PARAMETER
DDQ
(SSTL_2)
TEMPERATURE RANGE
REF
normally at
0 to +70 C
0 to +70 C
0 to +70 C
DDQ
C
V
L
CC
2
= 30 pF; V
= 2.5 V
PIN CONFIGURATION
CONDITIONS
DDQ
= 2.5 V
SSTV16857DGG
SSTV16857DGV
ORDER CODE
SSTV16857EV
V
V
V
V
V
GND
GND
GND
GND
GND
Q10
DDQ
DDQ
DDQ
DDQ
Q12
DDQ
Q13
Q14
Q11
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
TYPICAL
2.4
2.9
SW00685
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SSTV16857
D1
D2
GND
V
D3
D4
D5
D6
D7
CLK–
CLK+
V
GND
V
RESET
D8
D9
D10
D11
D12
V
GND
D13
D14
CC
CC
REF
CC
DWG NUMBER
SOT362-1
SOT480-1
SOT702-1
Product data
UNIT
pF
ns