IS43TR16640AL-15GBL-TR ISSI, IS43TR16640AL-15GBL-TR Datasheet
IS43TR16640AL-15GBL-TR
Specifications of IS43TR16640AL-15GBL-TR
Related parts for IS43TR16640AL-15GBL-TR
IS43TR16640AL-15GBL-TR Summary of contents
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... Note: Faster speed options are backward compatible to slower speed options. Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products ...
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... P VSS A5 R VDD A7 T VSS RESET# Note: NC balls have no internal connection. NC(A13), NC(A14) and NC(A15) are one of NC pins and reserved for higher densities Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 DQ0 DQS DQS# DQ4 RAS# ...
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... TDQS function via mode register A11 = 0 in MR1 Connect: No internal electrical connection is present. VDDQ Supply DQ Power Supply: 1.5 V +/- 0.075 V for standard voltage or 1.35V +0.1V, -0.067V for low voltage VSSQ Supply DQ Ground Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 3 ...
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... VREFDQ Supply Reference voltage for DQ VREFCA Supply Reference voltage for CA ZQ Supply Reference Pin for ZQ calibration Input only pins (BA0-BA2, A0-A13, RAS#, CAS#, WE#, CS#, CKE, ODT, and RESET#) do not supply termination. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 4 ...
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... Write Abbreviation Function ACT Active PRE Precharge PREA Precharge All MRS Mode Register Set REF Refresh ZQCL ZQ Calibration Long Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 MRS,MPR, Initialization Write Leveling ZQCL ZQCL ZQ ZQCS Idle Calibration ACT Active Activating ...
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... BA2, “High” to BA0 and BA1.) 8. Issue MRS Command to load MR1 with all application settings and DLL enabled. (To issue "DLL Enable" command, provide "Low" to A0, "High" to BA0 and "Low" to BA1 – BA2). Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 ...
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... CKE is pulled “LOW” before RESET being de-asserted (min. time 10 ns). 2. Follow Power-up Initialization Sequence steps 2 to 11. 3. The Reset sequence is now completed; DDR3 SDRAM is ready for normal operation. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 ...
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... The mode register set command cycle time, tMRD is required to complete the write operation to the mode register and is the minimum time required between two MRS commands shown as below. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 ...
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... Feature is disabled in the Mode Register prior and after an MRS command, the ODT Signal can be registered either LOW or HIGH before, during and after the MRS command. The mode registers are divided into various fields depending on the functionality and/or modes. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 ...
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... Accesses within a given burst may be programmed to sequential or interleaved order. The burst type is selected via bit A3 as shown in Figure 2.3.2. The ordering of accesses within a burst is determined by the burst length, burst type, and the starting column address as shown in Table below. The burst length is defined by bits A0-A1. Burst length options include Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 ...
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... Once the DLL is enabled, a subsequent DLL Reset should be applied. Any time that the DLL reset function is used, tDLLK must be met before any functions that require the DLL can be used (i.e., Read commands or ODT synchronous operations). 2.3.2.5 Write Recovery Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 burst type = Sequential ...
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... MR0 0 1 MR1 1 0 MR2 1 1 MR3 * 1 : A8, A10, and A13 must be programmed to 0 during MRS. * TDQS must be disabled for x16 option. 2.3.3.1 DLL Enable/Disable Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 A11 A10 Rtt 0* Level Rtt D ...
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... DQS, DQS#, etc.) are disconnected from the device, thus removing any loading of the output drivers. This feature may be useful when measuring module power, for example. For normal operation, A12 should be set to ‘0’. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 ...
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... Write command and the availability of the first bit of input data. DDR3 SDRAM does not support any half-clock latencies. The overall Write Latency (WL) is defined as Additive Latency (AL) + CAS Write Latency Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B ...
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... Power down mode, Self-Refresh and any other non-RD/RDA command is not allowed during MPR enable mode. The RESET function is supported during MPR enable mode. The Multi Purpose Register (MPR) function is used to Read out a predefined system timing calibration bit sequence. The basic concept of the MPR is shown in Figure 2.3.5.1. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 A12 ...
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... The RESET function is supported during MPR enable mode. MPR MR3 Register Definition MR3 A[2] MR3 A[1:0] MPR MPR-Loc don’t care ( See Table 13 Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 Memory Core (all banks precharged) MR3[A2] Register pre-defined DQ, DM, DQS, DQS# Figure 2.3.5.1 MPR Block Diagram Normal operation, no MPR transaction ...
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... Regular read latencies and AC timings apply. o DLL must be locked prior to MPR Reads. o NOTE: *) Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 Burst Read Address ...
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... NOTE: Good reference for the example of MPR feature is the JEDEC standard No.93-3D, 4.10.4 Protocol example. Relevant Timing Parameters AC timing parameters are important for operating the Multi Purpose Register: tRP, tMRD, tMOD, and tMPRR. For more details refer to “Electrical Characteristics & AC Timing” Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 18 ...
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... The Deselect command performs the same function as No Operation command. 12. Refer to the CKE Truth Table for more detail with CKE transition. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 ...
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... Deselect(DES) Command The Deselect function (CS# HIGH) prevents new commands from being executed by the DDR3 SDRAM. The DDR3 SDRAM is effectively deselected. Operations already in progress are not affected. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 Command (N) ...
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... Note: The tDQSCK is used here for DQS, DQS, and DQ to have a simplified diagram; the DLL_off shift will affect both timings in the same way and the skew between all DQ, DQS, and DQS# signals will still be tDQSQ Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B ...
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... Wait for tMOD, then DRAM is ready for next command (Remember to wait tDLLK after DLL Reset before applying command requiring a locked DLL!). In addition, wait also for tZQoper in case a ZQCL command was issued. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 ...
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... Once a don’t care, changing the clock frequency is permissible, provided the new clock frequency is stable prior to tCKSRX. When entering and exiting Self-Refresh mode for the sole purpose of changing the clock frequency, the Self-Refresh entry and exit specifications must still be met. ...
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... NOTE: In Write Leveling Mode with its output buffer disabled (MR1[bit7 with MR1[bit12 all RTT_Nom settings are allowed; in Write Leveling Mode with its output buffer enabled (MR1[bit7 with MR1[bit12 only RTT_Nom settings of RZQ/2, RZQ/4 and RZQ/6 are allowed. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B ...
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... CK, CK shown with solid dark line, where as CK# is drawn with dotted line. 6. DQS, DQS# needs to fulfill minimum pulse width requirements tDQSH(min) and tDQSL(min) as defined for regular Writes; the max pulse width is system dependent. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 ...
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... If the ASR mode is not enabled (MR2 bit.A6 = 0b), the SRT bit (MR2 A7) must be manually programmed with the operating temperature range required during Self-Refresh operation. Support of the ASR option does not automatically imply support of the Extended Temperature Range. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 ...
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... Supply Voltage for Output Notes: 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 Parameter Storage Temperature Parameter ...
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... VIH.DQ(AC150) AC input logic high VIL.DQ(AC150) AC input logic low Reference Voltage for VREFDQ(DC) DQ, DM inputs Reference Voltage for VREFDQ_t(DC) trained DQ, DM inputs Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 DDR3-800/1066/1333/1600 Parameter Min Vref + 0.100 VSS Vref + 0.175 Note 2 Vref + 0 ...
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... To allow VREFDQ margining, all DRAM Data Input Buffers MUST use external VREF (provided by system) as the input for their VREFDQ pins. All VIH/L input level MUST be compared with the external VREF level at the 1st stage of the Data input buffer Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B ...
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... Vref ac-noise. Timing and voltage effects due to ac-noise on Vref up to the specified limit (±1% of VDD) are included in DRAM timing and their associated de-ratings. Figure 4.2 Illustration of Vref(DC) tolerance and Vrefac-noise limits Voltage Vref(D Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 Vref ac-noise VDD ...
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... These values are not defined; however, the single-ended signals CK, CK#, DQS, DQS#, DQSL, DQSL#, DQSU, DQSU# need to be within the respective limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for overshoot and undershoot Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B ...
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... VIL(dc)min) for single-ended signals as well as the limitations for overshoot and undershoot. VDD or VDDQ VSEHmin VDD/2 or VDDQ/2 VSELmax VSS or VSSQ Figure 4.3.3 Single-ended requirement for differential signals. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 max ...
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... See “Address / Command Setup, Hold and Derating” for single-ended slew rate definitions for address and command signals. See “Data Setup, Hold and Slew Rate Derating” for single-ended slew rate definitions for data signals. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 ...
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... Differential input slew rate for falling edge (CK-CK# & DQS- DQS#) Note : The differential signal (i.e., CK-CK# & DQS-DQS#) must be linear between these thresholds. Figure 4.6.1 Input Nominal Slew Rate Definition for DQS, DQS# and CK, CK# Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 Measured ...
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... ASR enabled (for devices supporting ASR and Extended 1 0 Temperature Range). Self-Refresh power consumption is temperature dependent 1 1 Illegal Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 Allowed Operating Temperature Range for Self-Refresh Mode o Normal ( Normal and Extended ( ...
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... Single ended output slew rate for falling edge 5.3.2 Output Slew Rate (single-ended) Parameter Single-ended Output Slew Rate Note: SR: Slew Rate. Q: Query Output (like in DQ, which stands for Data-in, Query -Output). se: Single-ended signals. For Ron = RZQ/7 setting. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 Parameter Parameter ...
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... System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics. CK,CK# Figure 5.5 Reference Load for AC Timing and Output Slew Rate Integrated Silicon Solution, Inc. – ...
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... The individual pull-up and pull-down resistors (RONPu and RONPd) are defined as follows: RONPu = [VDDQ-Vout Iout | ------------------- under the condition that RONPd is turned off (1) RONPd = Vout / | Iout | -------------------------------under the condition that RONPu is turned off (2) Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 ...
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... DDR3L (assuming 1.35V RZQ = 240ohms; entire operating temperature range; after proper ZQ calibration) , RONNom Resistor RON34Pd 34 ohms RON34Pu 40 ohms RON40Pd 40 ohms RON40Pu Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 Chip in Drive Mode Output Driver I Pu RONPu RONPd I Pd Vout VOLdc=0 ...
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... RONPU@VOHdc 0.6 - dRONdTH*lDelta Tl - dRONdVH*lDelta Vl RON@VOMdc 0.9 - dRONdTM*lDelta Tl - dRONdVM*lDelta Vl RONPD@VOLdc 0.6 - dRONdTL*lDelta Tl - dRONdVL*lDelta Vl Note: dRONdT and dRONdV are not subject to production test but are verified by design and characterization. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 VOMdc=0.5xVDDQ VOHdc=0.8xVDDQ VOMdc= 0.5xVDDQ Min. ...
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... The following table provides an overview of the ODT DC electrical characteristics. The values for RTT60Pd120, RTT60Pu120, RTT120Pd240, RTT120Pu240, RTT40Pd80, RTT40Pu80, RTT30Pd60, RTT30Pu60, RTT20Pd40, RTT20Pu40 are not specification requirements, but can be used as design guide lines: Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 Max 1 ...
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... Apply VIH(ac) to pin under test and measure current I(VIH(ac)), then apply VIL(ac) to pin under test and measure current I(VIL(ac)) respectively. RTT = [VIH(ac) - VIL(ac)] / [I(VIH(ac)) - I(VIL(ac))] 6. Measurement definition for VM and DVM: Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 Resistor Vout VOLdc = 0 ...
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... Rising edge defined by the end point of ODTLcnw, t ADC ODTLcwn4, or ODTLcwn8 Reference Settings for ODT Timing Measurements Measured Parameter RTT_Nom Setting t AON t AONPD t AOFPD Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 max 1.6 + dRTTdT*lDelta Tl + dRTTdV*lDelta Vl Max 1.5 0.15 VDDQ DQ,DM DUT DQS, DQS#, ...
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... Figure 5.9.2.1 Definition of t AON CK CK# DQ,DM,DQS, DQS#,TDQS, TDQS# Figure 5.9.2.2 Definition of t AONPD CK CK# DQ,DM,DQS, DQS#,TDQS, TDQS# Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 RZQ/12 NA RZQ/12 RZQ/2 Begin Point : Rising edge of CK-CK# defined by the end of ODTLon t AON Tsw2 Tsw1 Vsw1 ...
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... DQ,DM,DQS, DQS#,TDQS, TDQS# Figure 5.9.2.4 Definition of t AOFPD CK CK# DQ,DM,DQS, DQS#,TDQS, TDQS# Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 Begin Point : Rising edge of CK-CK# with defined by the end point of ODTLoff t AOF V End Point : Extrapolated point at V RTT NOM ...
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... Begin Point : Rising edge of CK-CK# defined by the end point of ODTLcnw CK CK# End Point : Extrapolated DQ,DM,DQS, point at V DQS#,TDQS, RTT_NOM TDQS# Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 Begin Point : Rising edge of CK-CK# defined by the end point of ODTLcwn4 or ODTLcwn8 t t ADC ADC Tsw21 ...
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... A0-A13, BA0-BA2, RAS#, CAS# and WE# DI_ADD_CMD 10 (ADD_CMD) - 0.5*(C (CK)+C DI_ADD_CMD (DQ,DM) - 0.5*(C (DQS)+C (DQS#)) DIO 12. Maximum external load capacitance on ZQ pin: 5 pF. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 DDR3/DDR3 DDR3/DDR3 L-800 L -1066 Min Max Min Max DDR3 1.5 3 1.5 DDR3L 1.5 2.5 1.5 2 ...
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... Burst Refresh Current IDD6 Self-Refresh Current Normal Temperature Range (0-85°C) IDD6ET Self-Refresh Current: extended temperature range IDD6TC Auto Self-Refresh Current IDD7 All Bank Interleave Read Current Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 DDR3-1066 DDR3-1333 DDR3-1600 Max. Max. Max ...
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... Burst Refresh Current IDD6 Self-Refresh Current Normal Temperature Range (0-85°C) IDD6ET Self-Refresh Current: extended temperature range IDD6TC Auto Self-Refresh Current IDD7 All Bank Interleave Read Current Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 DDR3-1066 DDR3-1333 DDR3-1600 Max. Max. Max ...
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... IDD6 Self-Refresh Current Normal Temperature Range (0-85°C) IDD6ET Self-Refresh Current: extended temperature range IDD6TC Auto Self-Refresh Current IDD7 All Bank Interleave Read Current Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 DDR3-1066 DDR3-1333 Max. Max. TBD TBD TBD TBD ...
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... Burst Refresh Current IDD6 Self-Refresh Current Normal Temperature Range (0-85°C) IDD6ET Self-Refresh Current: extended temperature range IDD6TC Auto Self-Refresh Current IDD7 All Bank Interleave Read Current Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 DDR3-1066 DDR3-1333 Max. Max 100 ...
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... DLL is already locked. tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only. tJIT(per) and tJIT(per,lck) are not subject to production test. 8.1.5 Definition for tJIT(cc), tJIT(cc, Ick) Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 tCK(avg ...
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... All Bank Refresh to active/refresh cmd time Average periodic refresh interval Notes: 1. The permissible Tcase operating temperature is specified by temperature grade. The maximum Tcase unless A2 grade, for which the maximum is 105 C. 8.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin DDR3-1066MT/s ...
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... ACT to internal read or write delay PRE command period ACT to ACT or REF period ACT to PRE command period CWL =5 CL=5 CWL=6 CWL=7 CWL =5 CL=6 CWL=6 CWL=7 Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 DDR3/DDR3L-1333 9-9-9 (-15H) Symbol Min Max tAA 13.125 20 tRCD 13.125 ...
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... CWL =5 CWL=6 CL=7 CWL=7 CWL=8 CWL =5 CWL=6 CL=8 CWL=7 CWL=8 CWL =5 CWL=6 CL=9 CWL=7 CWL=8 CWL =5 CWL=6 CL=10 CWL=7 CWL =8 Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 tCK(AVG) Reserved tCK(AVG) 1.875 <2.5 tCK(AVG) Reserved tCK(AVG) Reserved tCK(AVG) 1.875 <2.5 tCK(AVG) 1.5 1.875 tCK(AVG) Reserved tCK(AVG) ...
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... CWL =5 CWL=6 CL=10 CWL=7 CWL =8 CWL CL=11 =5,6,7,8 CWL=5,6, 7,8 CL=12,13 CWL =9 Supported CL Settings Supported CWL Settings Note :In these tables in section 8.3, grey shading is for readability purposes only. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 tCK(AVG) Reserved tCK(AVG) Reserved tCK(AVG) Reserved tCK(AVG) 1.25 <1.5 5,6,7,8,9,10,11 5,6,7,8 DDR3/DDR3L-1866 12-12-12 (-107L) ...
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... Vih(ac) / Vil(ac) levels Data hold time from DQS, DQS# referenced to Vih(dc) / Vil(dc) levels DQ and DM Input pulse width for each input Data Strobe Timing DQS,DQS# differential READ Preamble Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 DDR3/DDR3L-800 Symbol Min. Max. ...
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... Command and Address hold time from CK, CK# referenced to Vih(dc) / Vil(dc) levels Command and Address setup time to CK, CK# referenced to Vih(ac) / Vil(ac) levels Control and Address Input pulse width for each input Calibration Timing Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 tRPST 0.3 Note tQSH ...
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... Timing of WRA command to Power Down entry (BL8OTF, BL8MRS, BC4OTF) Timing of WR command to Power Down entry (BC4MRS) Timing of WRA command to Power Down entry (BC4MRS) Timing of REF command to Power Down entry Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 tZQinit 512 - tZQoper 256 ...
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... Cycle to Cycle Period Jitter Cycle to Cycle Period Jitter during DLL locking period Duty Cycle Jitter Cumulative error across 2 cycles Cumulative error across 3 cycles Cumulative error across 4 cycles Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 tMRSPDENmin.: tMOD(min) tMRSPDEN tMRSPDENmax.: - ODTH4min.: 4 ODTH4 ODTH4max ...
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... DLL locking time Internal READ Command to PRECHARGE Command delay Delay from start of internal write transaction to internal read command WRITE recovery time Mode Register Set command cycle time Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 tERR(5per) -168 168 tERR(6per) ...
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... DLL frozen to commands not requiring a locked DLL Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL CKE minimum pulse width Command pass disable delay Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 tMODmin.: max(12nCK, 15ns) tMOD tMODmax.: ...
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... Write leveling output error 9.2.2 Timing Parameter by Speed Bin (DDR3-1866) Parameter Clock Timing Minimum Clock Cycle Time (DLL off mode) Average Clock Period Average high pulse width Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 tCPDEDmax.: - tPDmin.: tCKE(min) tPD tPDmax.: 9*tREFI tACTPDENmin ...
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... DQS and DQS# high-impedance time (Referenced from RL + BL/2) DQS, DQS# differential input low pulse width DQS, DQS# differential input high pulse width DQS, DQS# rising edge to CK, CK# rising Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 tCL(avg) 0.47 0.53 Min ...
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... DLL Minimum CKE low width for Self Refresh entry to exit timing Valid Clock Requirement after Self Refresh Entry (SRE) or Power-Down Entry (PDE) Valid Clock Requirement before Self Refresh Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 tDSS 0.18 - tDSH ...
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... Write leveling setup time from rising CK, CK# crossing to rising DQS, DQS# crossing Write leveling hold time from rising DQS, DQS# crossing to rising CK, CK# crossing Write leveling output delay Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 tCKSRXmax.: - tXPmin.: max(3nCK, 6ns) tXP tXPmax ...
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... SDRAM has tCK(avg),act=2500ps, tJIT(per),act,min = -72ps and tJIT(per),act,max = 93ps, then tRPRE,min(derated) = tRPRE,min + tJIT(per),act,min = 0.9 x tCK(avg),act + tJIT(per),act,min = 0.9 x 2500ps - 72ps = 2178ps. Similarly, tQH,min(derated) = tQH,min + tJIT(per),act,min = 0.38 x tCK(avg),act + tJIT(per),act,min = 0.38 x 2500ps - 72ps = 878ps. (Caution on the min/max usage!) Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 tWLOE ...
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... This row defines 38 parameters. 25. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 68 ...
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... Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 69 ...
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... The tIS(base) AC150 specifications are adjusted from the tIS(base) AC175 specification by adding an additional 125 ps for DDR3-800/1066 or 100ps for DDR3-1333/1600 of derating to accommodate for the lower alternate threshold of 150 mV and another account for the earlier reference point [(175 mv - 150 mV V/ns]. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 ...
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... Required time tVAC above VIH(ac) {below VIL(ac)} for valid transition Slew Rate [V/ns] > 2.0 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 < 0.5 Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 ” tIS, ” tIH derating in [ps] AC/DC based CK,CK# Differential Slew Rate 2.0 V/ns 1.8 V/ns ” tIH ” tIS ” tIH ” tIS ” tIH ” ...
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... VIH(dc)MIN tangent line VREF(dc) [VIH(ac)min-VREF(dc)] VIL(dc)MAX VIL(ac)MAX Normal slew rate tVAC V SS ∆TF Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 CK# CK tIS tIH V DDQ tVAC VIH(ac)MIN VIH(dc)MIN Normal VREF(dc) slew rate ...
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... Data Setup and Hold Base-Values Symbol Reference tDS(base) AC175 VIH/L(ac) tDS(base) AC150 VIH/L(ac) tDH(base) DC100 VIH/L(dc) NOTE: (ac/dc referenced for 1V/ns DQ-slew rate and 2 V/ns DQS slew rate) Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 DDR3-800 DDR3-1066 DDR3-1333 75 25 125 75 150 ...
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... Required time tVAC above VIH(ac) {below VIL(ac)} for valid transition Slew Rate [V/ns] Slew Rate [V/ns] min > 2.0 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 < 0.5 Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 tDS, DH derating in [ps] AC/DC based A A DQS, DQS# Differential Slew Rate 2.0 V/ns 1.8 V/ns AtDS AtDH AtDS AtDH AtDS ...
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... VREF(dc) tangent Setup slew Rate @ line VIL(dc)MAX [VIH(ac)min-VREF(dc)] VIL(ac)MAX Normal slew rate ∆TR tVAC V SS ∆TF Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 DQS# DQS V tDS tDH DDQ tVAC VIH(ac)MIN VIH(dc)MIN Normal VREF(dc) ...
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... Automotive, A2 Range: (–40°C ≤ T Data Rate CL-tRCD-tRP 1066MT/s 7-7-7 1333MT/s 8-8-8 1333MT/s 9-9-9 1600MT/s 10-10-10 Note: Contact ISSI for availability of options. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 ≤ 95°C) C Order Part No. IS43TR16640A -15GBL IS43TR16640A -125JBL ≤ 95°C) C Order Part No. IS43TR16640A -15GBLI IS43TR16640A -125JBLI ≤ ...
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... Automotive, A2 Range: (–40°C ≤ T Data Rate CL-tRCD-tRP 1333MT/s 8-8-8 1600MT/s 10-10-10 Note: Contact ISSI for availability of options. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 ≤ 95°C) C Order Part No. IS43TR81280A -15GBL IS43TR81280A -125JBL ≤ 95°C) C Order Part No. ...
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... IS43/46TR16640A, IS43/46TR16640AL IS43/46TR81280A , IS43/46TR81280AL Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 78 ...
Page 79
... IS43/46TR16640A, IS43/46TR16640AL IS43/46TR81280A , IS43/46TR81280AL Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00B 11/21/2012 79 ...