STMPE812ABJR STMicroelectronics, STMPE812ABJR Datasheet - Page 9

• Manufacturer Part Number: STMPE812ABJR
• Description: Touch Screen Converters & Controllers Touchscreen cntrlr S-Touch
• Manufacturer: STMicroelectronics
• Type: Resistive Touch Controllersr

Specifications of STMPE812ABJR

• Rohs: yes
• Input Type: 1 TSC
• Data Rate: 400 kbps
• Resolution: 12 bit
• Interface Type: 4-wire, I2C
• Supply Voltage: 1.65 V to 3.6 V
• Supply Current: 100 uA
• Operating Temperature: - 40 C to + 85 C
• Package / Case: CSP-12
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 1.65 V

STMPE812A
2.1
2.2
I
The features that are supported by the I
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The slave address is selected by the state of P0 pin. The state of the pin is read upon reset
and then the pin can be configured for normal operation. The pin shall have an external pull-
up or pull-down to set the address.
Table 4.
Start condition
A Start condition is identified by a falling edge of SDATA while SCLK is stable at high state.
A Start condition must precede any data/command transfer. The device continuously
monitors for a Start condition and does not respond to any transaction unless one is
encountered.
Stop condition
A Stop condition is identified by a rising edge of SDATA while SCLK is stable at high state. A
Stop condition terminates communication between the slave device and the bus master. A
read command that is followed by NoAck can be followed by a Stop condition to force the
slave device into idle mode. When the slave device is in idle mode, it is ready to receive the
next I
operation to registers.
Acknowledge bit
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter
releases the SDATA after sending eight bits of data. During the ninth bit, the receiver pulls
the SDATA low to acknowledge the receipt of the eight bits of data. The receiver may leave
the SDATA in high state if it does not acknowledge the receipt of the data.
Data input
The device samples the data input on SDATA on the rising edge of the SCLK. The SDATA
signal must be stable during the rising edge of SCLK and the SDATA signal must change
only when SCLK is driven low.
2
C features
I
Operates at V
Compliant to Philips I
Supports standard (up to 100 Kbps) and fast (up to 400 Kbps) modes
I
bit)
2
2
2
C slave device
C address in 0x41 (0x82/83 including Rd/Wr bit) or 0x40 (0x80/81 including Rd/Wr
C transaction. A Stop condition at the end of a write command stops the write
Slave address
ADDR (P0)
CC
(1.65 V - 3.6 V)
0
1
2
C specification version 2.1
Doc ID 18225 Rev 4
2
C interface are listed below:
7-bit I
2
C slave address
40h
41h
I2C interface
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