SSTUH32865ET/G,551 NXP Semiconductors, SSTUH32865ET/G,551 Datasheet - Page 8

IC REG BUFFER 28-BIT 160TFBGA

SSTUH32865ET/G,551

Manufacturer Part Number
SSTUH32865ET/G,551
Description
IC REG BUFFER 28-BIT 160TFBGA
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SSTUH32865ET/G,551

Logic Type
1:2 Registered Buffer with Parity
Supply Voltage
1.7 V ~ 1.9 V
Number Of Bits
28
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
160-TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-3578
935277963551
SSTUH32865ET/G-S

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SSTUH32865ET/G,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
7. Functional description
Table 3:
[1]
Table 4:
[1]
9397 750 14136
Product data sheet
RESET
RESET
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Q
PARIN arrives one clock cycle after the data to which it applies. All Dn inputs must be driven to a known state for parity to be calculated
correctly.
L
H
H
H
H
H
H
H
H
H
H
L
0
is the previous state of the associated output.
Function table (each flip-flop)
Parity and standby function table
floating
DCS0
X or floating
X or
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
DCS0
7.1 Function table
H
H
H
H
H
X
L
L
L
L
floating
DCS1
X or
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
X or floating
DCS1
H
H
H
H
H
X
L
L
L
L
CSGATEEN
X or floating
Inputs
H
H
H
X
X
X
X
X
X
X
X
X
L
L
L
X or floating
L or H
CK
Inputs
Rev. 01 — 11 March 2005
floating
L or H
L or H
L or H
L or H
L or H
X or
CK
1.8 V high output drive DDR registered buffer with parity
X or floating
L or H
floating
CK
L or H
L or H
L or H
L or H
L or H
X or
CK
Dn, DODTn,
X or floating
DCKEn
(D0 to D21)
X or floating
of inputs = H
H
H
H
H
H
X
X
X
X
X
L
L
L
L
L
even
even
even
even
odd
odd
odd
odd
X
X
Qn
Q
Q
Q
Q
Q
Q
Q
H
H
H
H
L
L
L
L
L
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
0
0
0
0
0
0
0
SSTUH32865
X or floating
PARIN
QCS0
Q
Q
Q
Q
Q
H
H
H
H
H
H
L
L
L
L
L
H
H
H
H
L
L
L
L
X
X
0
0
0
0
0
Outputs
[1]
QCS1
Q
Q
Q
Q
Q
H
H
H
H
H
H
L
L
L
L
L
0
0
0
0
0
PTYERR
[1]
PTYERR
PTYERR
Output
QODTn,
QCKEn
H
H
H
H
H
L
L
L
L
Q
Q
Q
Q
Q
H
H
H
H
H
L
L
L
L
L
L
[2] [3]
8 of 28
0
0
0
0
0
0
0

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