DS3231S#-W Maxim Integrated, DS3231S#-W Datasheet - Page 17

• Manufacturer Part Number: DS3231S#-W
• Description: Real Time Clock
• Manufacturer: Maxim Integrated
• Series: DS3231r

Specifications of DS3231S#-W

• Part # Aliases: 90-3231S#W00

The DS3231 can operate in the following two modes:
Figure 5. Data Write/Read (Write Pointer, Then Read)—Slave Receive and Transmit
Maxim Integrated
master returns an acknowledge bit after all received
bytes other than the last byte. At the end of the last
received byte, a not acknowledge is returned.
The master device generates all the serial clock puls-
es and the START and STOP conditions. A transfer is
ended with a STOP condition or with a repeated
START condition. Since a repeated START condition
is also the beginning of the next serial transfer, the
bus will not be released. Data is transferred with the
most significant bit (MSB) first.
Slave receiver mode (DS3231 write mode): Serial
data and clock are received through SDA and SCL.
After each byte is received, an acknowledge bit is
transmitted. START and STOP conditions are recog-
nized as the beginning and end of a serial transfer.
Address recognition is performed by hardware after
reception of the slave address and direction bit. The
slave address byte is the first byte received after the
master generates the START condition. The slave
address byte contains the 7-bit DS3231 address,
which is 1101000, followed by the direction bit (R/W),
which is 0 for a write. After receiving and decoding
the slave address byte, the DS3231 outputs an
acknowledge on SDA. After the DS3231 acknowl-
edges the slave address + write bit, the master
transmits a word address to the DS3231. This sets
the register pointer on the DS3231, with the DS3231
S - START
Sr - REPEATED START
A - ACKNOWLEDGE (ACK)
P - STOP
A - NOT ACKNOWLEDGE (NACK)
R/W - READ/WRITE OR DIRECTION BIT ADDRESS
XXXXXXXX
<DATA (n)>
S
ADDRESS>
1101000
<SLAVE
Extremely Accurate I
<R/W>
A
0
A
<DATA (n + 1)>
XXXXXXXX
<WORD ADDRESS (n)>
MASTER TO SLAVE
XXXXXXXX
A
A
<DATA (n + 2)>
<SLAVE ADDRESS (n)>
XXXXXXXX
Sr
SLAVE TO MASTER
1101000
acknowledging the transfer. The master may then
transmit zero or more bytes of data, with the DS3231
acknowledging each byte received. The register
pointer increments after each data byte is trans-
ferred. The master generates a STOP condition to
terminate the data write.
Slave transmitter mode (DS3231 read mode): The
first byte is received and handled as in the slave
receiver mode. However, in this mode, the direction
bit indicates that the transfer direction is reversed.
Serial data is transmitted on SDA by the DS3231
while the serial clock is input on SCL. START and
STOP conditions are recognized as the beginning
and end of a serial transfer. Address recognition is
performed by hardware after reception of the slave
address and direction bit. The slave address byte is
the first byte received after the master generates a
START condition. The slave address byte contains
the 7-bit DS3231 address, which is 1101000, fol-
lowed by the direction bit (R/W), which is 1 for a
read. After receiving and decoding the slave
address byte, the DS3231 outputs an acknowledge
on SDA. The DS3231 then begins to transmit data
starting with the register address pointed to by the
register pointer. If the register pointer is not written to
before the initiation of a read mode, the first address
that is read is the last one stored in the register point-
er. The DS3231 must receive a not acknowledge to
end a read.
A
<R/W>
1
...
RTC/TCXO/Crystal
NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK.
A
<DATA (n + X)>
XXXXXXXX
(X + 1 BYTES + ACKNOWLEDGE)
DATA TRANSFERRED
2
C-Integrated
A
P
DS3231
17