DS3231S#-W Maxim Integrated, DS3231S#-W Datasheet - Page 16

no-image

DS3231S#-W

Manufacturer Part Number
DS3231S#-W
Description
Real Time Clock
Manufacturer
Maxim Integrated
Series
DS3231r
Datasheet

Specifications of DS3231S#-W

Part # Aliases
90-3231S#W00

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DS3231S#-WDS3231S
Manufacturer:
MAXIM
Quantity:
225
Company:
Part Number:
DS3231S#-WDS3231S
Manufacturer:
MAXIM
Quantity:
18 500
Company:
Part Number:
DS3231S#-WDS3231S
Manufacturer:
MAX
Quantity:
20 000
Company:
Part Number:
DS3231S#-WDS3231S#
Manufacturer:
AVAGO
Quantity:
15
Company:
Part Number:
DS3231S#-WDS3231S#
Manufacturer:
MAXIM/美信
Quantity:
20 000
Extremely Accurate I
RTC/TCXO/Crystal
Figures 3 and 4 detail how data transfer is accom-
plished on the I
the R/W bit, two types of data transfer are possible:
DS3231
Figure 2. I
Figure 3. Data Write—Slave Receiver Mode
Figure 4. Data Read—Slave Transmitter Mode
16
Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master is
slave by not generating an acknowledge bit on the
last byte that has been clocked out of the slave. In
this case, the slave must leave the data line high to
enable the master to generate the STOP condition.
SDA
SCL
2
C Data Transfer Overview
S - START
A - ACKNOWLEDGE (ACK)
P - STOP
R/W - READ/WRITE OR DIRECTION BIT ADDRESS
S - START
A - ACKNOWLEDGE (ACK)
P - STOP
A - NOT ACKNOWLEDGE (NACK)
R/W - READ/WRITE OR DIRECTION BIT ADDRESS
S
S
ADDRESS>
ADDRESS>
1101000
1101000
<SLAVE
<SLAVE
2
C bus. Depending upon the state of
MSB
1
0
1
<R/W>
<R/W>
A
A
2
<WORD ADDRESS (n)>
SLAVE ADDRESS
MASTER TO SLAVE
XXXXXXXX
<DATA (n)>
XXXXXXXX
SLAVE TO MASTER
6
A
A
7
<DATA (n + 1)>
SLAVE TO MASTER
DIRECTION
XXXXXXXX
XXXXXXXX
<DATA (n)>
2
R/W
BIT
8
MASTER TO SLAVE
C-Integrated
SIGNAL FROM RECEIVER
ACKNOWLEDGEMENT
NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK.
ACK
9
A
A
the slave address. Next follows a number of data
bytes. The slave returns an acknowledge bit after
each received byte. Data is transferred with the most
significant bit (MSB) first.
Data transfer from a slave transmitter to a master
receiver. The first byte (the slave address) is trans-
mitted by the master. The slave then returns an
acknowledge bit. Next follows a number of data
bytes transmitted by the slave to the master. The
(X + 1 BYTES + ACKNOWLEDGE)
(X + 1 BYTES + ACKNOWLEDGE)
<DATA (n + 2)>
<DATA (n + 1)>
XXXXXXXX
XXXXXXXX
DATA TRANSFERRED
DATA TRANSFERRED
1
A
A
2
...
...
3–7
<DATA (n + X)>
<DATA (n + X)
XXXXXXXX
XXXXXXXX
SIGNAL FROM RECEIVER
ACKNOWLEDGEMENT
8
ACK
9
A
A
P
P
Maxim Integrated

Related parts for DS3231S#-W