9E4101AFILF IDT, 9E4101AFILF Datasheet
9E4101AFILF
Specifications of 9E4101AFILF
Related parts for 9E4101AFILF
9E4101AFILF Summary of contents
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... Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2. FS_B and FS_A are low-threshold inputs. Please see the V specifications in the Input/Supply/Common Output Parameters Table for correct values. Programmable Timing Control Hub IDT TM TM for Intel Systems Features/Benefits: • ...
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... SRCCLKT2 23 SRCCLKC2 24 SRCCLKT3 25 SRCCLKC3 26 SRCCLKT4_SATA 27 SRCCLKC4_SATA 28 VDDSRC Programmable Timing Control Hub TM IDT TM for Intel Systems PIN TYPE PWR Power supply for PCI clocks, nominal 3.3V PWR Ground pin. OUT PCI clock output. OUT PCI clock output. OUT PCI clock output. PWR Ground pin. ...
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... GND 52 REFOUT 53 FS_C/TEST_SEL 54 PCICLK0 55 PCICLK1 56 PCICLK2 Programmable Timing Control Hub TM IDT TM for Intel Systems TYPE PWR Ground pin. OUT Complement clock of differential SRC clock pair. OUT True clock of differential SRC clock pair. OUT Complement clock of differential SRC clock pair. OUT True clock of differential SRC clock pair. ...
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... VDD GND 48 51 1,7 2,6 21,28, Master clock, CPU Analog 11 13 DOT, USB, PLL_48 42 45 Programmable Timing Control Hub TM IDT TM for Intel Systems Frequency PLL2 Programmable Programmable Spread Frequency PLL1 Description Xtal, Ref PCICLK outputs SRCCLK outputs CPUCLK clocks for Intel Systems TM 4 Dividers ...
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... Beginning Byte = N Data Byte Count = X Beginning Byte N Byte stoP bit Programmable Timing Control Hub TM IDT TM for Intel Systems How to Read: • Controller (host) will send start bit. • Controller (host) sends the write address D2 (H) • ICS clock will acknowledge • ...
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... Bit 7 Bit 6 14,15 DOT_96MHz 10 Bit 5 Bit Bit 3 Bit 2 Bit 1 Bit 0 Programmable Timing Control Hub TM IDT TM for Intel Systems Name Control Function Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable RESERVED Name Control Function Output Enable ...
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... Bit 6 Bit Bit 4 Bit Bit 2 Bit Bit 0 Programmable Timing Control Hub TM IDT TM for Intel Systems Name Control Function Drive Mode in PCI_Stop RESERVED RESERVED RESERVED Drive Mode in PD Drive Mode in PD Drive mode in PD CPUCLK1 Drive mode in PD CPUCLK0 Name Control Function ...
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... C Table: Spread Spectrum Control Register Byte 13 Pin # Bit 7 - Bit 6 - Bit 5 - Bit 4 - Bit 3 - Bit 2 - Bit Bit 0 Programmable Timing Control Hub TM IDT TM for Intel Systems Name Control Function RESERVED RESERVED RESERVED WD4 Enables WD3 prograaming bytes WD2 10-19 WD1 WD0 Name Control Function M/N Programming M/NEN Enable ...
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... Pin # - Bit 7 Bit Bit 5 Bit Bit 3 Bit Bit 1 Bit 0 - Programmable Timing Control Hub TM IDT TM for Intel Systems Name Control Function RESERVED RESERVED SSP13 It is recommended SSP12 to use ICS Spread SSP11 % table for spread SSP10 programming. SSP9 SSP8 Name Control Function SRC Div3 ...
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... I C Table: Slew Rate Control Register Byte 23 Pin # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Programmable Timing Control Hub TM IDT TM for Intel Systems Name Control Function RESERVED RESERVED RESERVED RESERVED PCI_Skw3 PCI_Skw2 PCI Skew Control PCI_Skw1 PCI_Skw0 Name Control Function ...
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... Bit 6 Bit Bit 4 Bit Bit 2 Bit Bit 0 Programmable Timing Control Hub TM IDT TM for Intel Systems Name Control Function RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Test Function ICS ONLY TEST ICS ONLY TEST ICS ONLY TEST ICS ONLY TEST ...
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... Guaranteed by design and characterization, not 100% tested in production. 2 See timing diagrams for timing requirements. 3 Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm accuracy on PLL outputs. Programmable Timing Control Hub TM IDT TM for Intel Systems Min GND - 0.5 -65 -40 2000 ...
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... Skew sk4 Jitter, Cycle to cycle t jcyc-cyc 1 Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFoutput is at 14.31818MHz Programmable Timing Control Hub TM IDT TM for Intel Systems =2pF, R =33 =49 REF CONDITIONS ...
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... Skew t sk3 Jitter, Cycle to cycle t jcyc-cyc 1 Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFoutput is at 14.31818MHz Programmable Timing Control Hub TM IDT TM for Intel Systems =2pF, R =33 =49 REF CONDITIONS ...
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... Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFoutput is at 14.31818MHz Programmable Timing Control Hub TM IDT TM for Intel Systems = 30 pF (unless otherwise specified) L CONDITIONS see Tperiod min-max values 33.33MHz output nominal 33 ...
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... Output Low Current I OL Rise Time t Fall Time t Skew t sk1 Duty Cycle d Jitter t jcyc-cyc 1 Guaranteed by design, not 100% tested in production. Programmable Timing Control Hub TM IDT TM for Intel Systems =2pF, R =33 =49 REF CONDITIONS MIN 3000 O x Statistical measurement 660 on single ended signal ...
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... If TEST is selected by B6b6, only B6b7 controls TEST_MODE. The FS_B/TEST_Mode pin is not used. · Power must be cycled to exit TEST. B6b6: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION) B6b7: 1= REF/N, Default = 0 (HI-Z) Programmable Timing Control Hub TM IDT TM for Intel Systems HW FS_C/TEST FS_B/TEST _SEL HW PIN ...
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... Programmable Timing Control Hub INDEX INDEX AREA AREA 45° 45° Ordering Information 9E4101yFILFT Example: XXXX Programmable Timing Control Hub TM IDT TM for Intel Systems c SYMBOL VARIATIONS - SEATING ...
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... Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners ...