9P935AGLF IDT, 9P935AGLF Datasheet - Page 9

• Manufacturer Part Number: 9P935AGLF
• Description: Delay Lines / Timing Elements
• Manufacturer: IDT

Specifications of 9P935AGLF

• Product Category: Delay Lines / Timing Elements
• Rohs: yes
• Part # Aliases: ICS9P935AGLF

Notes:
1.
2.
3.
4.
5.
6.
IDT
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D4
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
ICS9P935
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
TM
WR
/ICS
Byte N + X -1
(see Note 2)
P
T
Beginning Byte N
Data Byte Count = X
Index Block Write Operation
Slave Address D4
Beginning Byte = N
Byte N + X - 1
Controller (Host)
Read-Back will support SMBus block read protocol.
be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred.
The Command code and Byte count shown above must be sent, The data is loaded until a Stop sequence is issued.
The IDT clock generator is a slave/receiver, I
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I
At power-on, all registers are set to a default condition, as shown.
TM
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
starT bit
stoP bit
WRite
General I
(H)
ICS (Slave/Receiver)
2
ACK
ACK
ACK
ACK
ACK
C serial interface information for the ICS9P935
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must
2
(H)
C component. It can read back the data stored in the latches for verification.
9
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D4
• ICS clock will acknowledge
• Controller (host) sends the begining byte
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D5
• ICS clock will acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock sends Byte 0 through byte X (if X
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
location = N
was written to byte 8)
WR
RD
RT
N
P
T
Index Block Read Operation
Slave Address D4
Beginning Byte = N
Slave Address D5
Controller (Host)
Not acknowledge
ACK
ACK
Repeat starT
starT bit
stoP bit
WRite
ReaD
(H)
(H)
ICS (Slave/Receiver)
Data Byte Count = X
.
Beginning Byte N
Byte N + X - 1
ACK
ACK
ACK
ICS9P935
REV H 12/1/08
(H)
(H)
(H)