74FCT388915TEJG8 IDT, 74FCT388915TEJG8 Datasheet
74FCT388915TEJG8
Specifications of 74FCT388915TEJG8
Related parts for 74FCT388915TEJG8
74FCT388915TEJG8 Summary of contents
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... SYNC (1) REF_SEL PLL_EN FREQ_SEL OE/RST The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE © 2004 Integrated Device Technology, Inc. 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE) DESCRIPTION: The FCT388915T uses phase-lock loop technology to lock the fre- quency and phase of outputs to the input reference clock ...
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... IDT74FCT388915T 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE) PIN CONFIGURATION 1 GND OE/RST 5 FEEDBACK 6 REF_SEL 7 SYNC( (AN GND(AN) 10 SYNC( FREQ_SEL GND SSOP TOP VIEW PIN DESCRIPTION Pin Name I/O SYNC(0) I Reference clock input SYNC(1) I Reference clock input ...
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... IDT74FCT388915T 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE) ABSOLUTE MAXIMUM RATINGS Symbol Description V (2) Terminal Voltage with Respect to GND TERM (3) V Terminal Voltage with Respect to GND TERM (4) V Terminal Voltage with Respect to GND TERM T Storage Temperature STG I DC Output Current OUT NOTES: 1 ...
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... IDT74FCT388915T 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE) POWER SUPPLY CHARACTERISTICS Symbol Parameter ΔI Quiescent Power Supply Current CC TTL Inputs HIGH (4) I Dynamic Power Supply Current CCD C Power Dissipation Capacitance PD (6) I Total Power Supply Current C NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. ...
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... Parameter t Rise/Fall Time RISE/FALL All Outputs (between 0.8V and 2V) PULSE WIDTH (3) t Output Pulse Width Q, Q, Q/2 outputs (3) Q0-Q4, Q5, Q/2, @ 1.5V t Output Pulse Width PULSE WIDTH (3) 2Q Output 2Q @ 1.5V t SYNC input to FEEDBACK delay PD (3) SYNC-FEEDBACK (measured at SYNC0 or 1 and FEEDBACK input pins Output to Output Skew between outputs 2Q, Q0-Q4, ...
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... All loop filter and analog isolation components should be tied as close to the package as possible. Stray current passing through the parasitics of long traces can cause undesirable voltage transients at the LF pin. b. The 10µF low frequency bypass capacitor and the 0.1µF high frequency bypass capacitor form a wide bandwidth filter that will minimize the 388915T's sensitivity to voltage transients from the system digital V supply and ground planes ...
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... IDT74FCT388915T 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE) The frequency relationship shown here is applicable to all Q outputs (Q0, Q1, Q2, Q3 and Q4). 1:2 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP In this application, the Q/2 output is connected to the FEEDBACK input. The internal PLL will line up the positive edges of Q/2 and SYNC, thus the Q/2 frequency will equal the SYNC frequency ...
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... IDT74FCT388915T 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE) CLOCK @ f SYSTEM CLO DISTRIBUTE CLO CLOCK @ 2f at point of use Figure 4. Multiprocessing Application Using the FCT388915T for Frequency Multiplication FCT388915T SYSTEM LEVEL TESTING FUNCTIONALITY When the PLL_EN pin is LOW, the PLL is bypassed and the FCT388915T is in low frequency " ...
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... IDT74FCT388915T 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE) TEST CIRCUITS AND WAVEFORMS Pulse D.U.T. Generator Ω Ω Ω Ω Ω / SYNC IN PUT (SYNC ( CYCLE SYNC IN PUT SYNC (0 FEED BAC K INPUT Q/2 OUTPUT ...
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... COMMERCIAL TEMPERATURE RANGE Plastic Leaded Chip Carrier PLCC - Green Small Shrink Outline IC SSOP - Green (1) 70MHz Max. Frequency (1) 100MHz Max. Frequency (1) 133MHz Max. Frequency (1) 150MHz Max. Frequency 3.3V Low skew PLL-based CMOS clock driver 0°C to +70°C for Tech Support: clockhelp@idt.com ...