91857AGLF IDT, 91857AGLF Datasheet

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91857AGLF

Manufacturer Part Number
91857AGLF
Description
Clock Drivers & Distribution
Manufacturer
IDT
Datasheet

Specifications of 91857AGLF

Product Category
Clock Drivers & Distribution
Rohs
yes
Part # Aliases
ICS91857AGLF
Value SSTL_2 Clock Driver (60MHz - 220MHz)
Recommended Application:
Zero delay board fan-out memory modules
Product Description/Features:
Switching Characteristics:
Functionality
0494C—08/15/05
A
n (
n (
n (
n (
n (
G
G
2
2
2
2
2
V
5 .
5 .
5 .
5 .
5 .
o
o
o
o
o
N
N
D
m
m
m
m
m
D
D
V
V
V
V
V
D
)
)
)
)
)
Meets PC3200 specification for DDRI-400 support
Low skew, low jitter PLL clock driver
1 to 10 differential clock distribution (SSTL_2)
Feedback pins for input to output synchronization
PD# for power management
Spread Spectrum tolerant inputs
Auto PD when input signal removed
CYCLE - CYCLE jitter (>100MHz):<75ps
OUTPUT - OUTPUT skew: <100ps
P
X
D
H
H
L
L
H
H
#
N I
C
L
P
K
U
L
H
L
H
L
H
_
T
N I
<
S
2
T
0
M
H
Integrated
Circuit
Systems, Inc.
C
) z
L
(
) 1
K
H
H
H
L
L
L
_
N I
C
C
L
H
Z
Z
H
Z
L
L
K
T
C
L
H
Z
Z
H
Z
L
L
K
C
O
F
U
B
T
_
P
O
H
Z
Z
H
Z
L
L
U
U
T
T
S
T
F
B
_
O
H
Z
Z
H
Z
L
L
U
T
C
B
B
P
y
y
L
p
p
a
a
L
s s
s s
o
o
o
o
o
S
f f
f f
n
n
f f
e
e
a t
d
d
e t
o /
o /
f f
f f
Block Diagram
CLK_INC
CLK_INT
FB_INC
FB_INT
PD#
CLK_INC
CLK_INT
CLKC0
CLKC1
CLKC2
CLKC3
CLKC4
CLKT0
CLKT1
CLKT2
CLKT3
CLKT4
6.10 mm. Body, 0.50 mm. pitch TSSOP
AGND
AVDD
GND
GND
GND
GND
GND
VDD
VDD
VDD
VDD
VDD
Control
Logic
PLL
Pin Configuration
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
48-Pin TSSOP
ICS91857
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
CLKC5
CLKT5
VDD
CLKT6
CLKC6
GND
GND
CLKC7
CLKT7
VDD
PD#
FB_INT
FB_INC
VDD
FB_OUTC
FB_OUTT
GND
CLKC8
CLKT8
VDD
CLKT9
CLKC9
GND
FB_OUTT
FB_OUTC
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT5
CLKC5
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
CLKC9

Related parts for 91857AGLF

91857AGLF Summary of contents

Page 1

Integrated Circuit Systems, Inc. Value SSTL_2 Clock Driver (60MHz - 220MHz) Recommended Application: Zero delay board fan-out memory modules Product Description/Features: • Meets PC3200 specification for DDRI-400 support • Low skew, low jitter PLL clock driver • ...

Page 2

ICS91857 Pin Descriptions ...

Page 3

Absolute Maximum Ratings Supply Voltage (VDD & AVDD -0.5V to 4.6V Logic Inputs . . . . . . . . . . . . . . . . . ...

Page 4

ICS91857 Electrical Characteristics for DDRI-400 - Input/Supply/Common Output Parameters 70°C; Supply Voltage A A VDD PARAMETER SYMBOL Input High Current I IH Input Low Current I IL Operating Supply I DD2.5 Current I DDPD Output High ...

Page 5

Recommended Operating Condition for DDR200/266/333 (see note1 85°C; Supply Voltage AVDD, VDD = 2.5V ± 0.2V (unless otherwise stated) A PARAMETER SYMBOL Supply Voltage DDQ Low level input voltage V IL High level ...

Page 6

ICS91857 Recommended Operating Condition for DDRI-400 (see note1 70°C; Supply Voltage AVDD, VDD = 2.6V ± 0.1V A PARAMETER SYMBOL Supply Voltage DDQ Low level input voltage V IL High level input voltage ...

Page 7

Timing Requirements for DDR200/266/333 70°C; Supply Voltage A A VDD PARAMETER Max clock frequency Application Frequency Range Input clock duty cycle CLK stabilization Timing Requirements for DDRI-400 70°C; Supply Voltage A A ...

Page 8

ICS91857 Switching Characteristics for DDRI-400 PARAMETER SYMBOL Low-to high level propagation delay time High-to low level propagation delay time Output enable time Output disable time Period jitter Half-period jitter Input clock slew rate Output clock slew rate 1 T Cycle ...

Page 9

VDD/2 ICS91857 -VDD/2 NOTE: V (TT) = GND Y , FBOUTC FBOUTT X 0494C—08/15/05 Parameter Measurement Information (CLKC) ICS91857 GND Figure 1. IBIS Model Output Load -VDD 10Ω ...

Page 10

ICS91857 CLK_INC CLK_INT FB_INC FB_INT FB_OUTC FB_OUTT FB_OUTC FB_OUTT FB_OUTC FB_OUTT X 0494C—08/15/05 Parameter Measurement Information t ( ...

Page 11

Y , FB_OUTC FB_OUTT X 20% Clock Inputs and Outputs 0494C—08/15/05 Parameter Measurement Information t (hper_n) t (hper_n+ (jit_Hper) (jit_Hper_n) 2xf O Figure 7. Half-Period Jitter 80% t slrr(i) ...

Page 12

ICS91857 INDEX INDEX AREA AREA 6.10 mm. Body, 0.50 mm. pitch TSSOP (20 mil) (240 mil) Ordering Information ICS91857yGLFT Example: ICS XXXX PPP - ...

Page 13

INDEX INDEX AREA AREA 4.40 mm. Body, 0.40 mm. pitch TSSOP (TVSOP) (16 mil) (173 mil) Ordering Information ICS91857yLLFT Example: ICS XXXX PPP - ...

Page 14

ICS91857 Revision History Rev. Issue Date Description C 8/15/2005 Added LF Ordering Information. 0494C—08/15/05 14 Page # 12-13 ...

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