DS2153QN-A7 Maxim Integrated, DS2153QN-A7 Datasheet - Page 48

Manufacturer Part Number

DS2153QN-A7

Description

In Stock

Manufacturer

Maxim Integrated

Datasheet

1.DS2153QA7.pdf (60 pages)

Figure 14-5. Transmit Side Timing

Figure 14-6. Transmit Side Boundary Timing

NOTE 1: TSYNC IS IN THE INPUT MODE (TCR1.0 = 0).

NOTE 2: TSYNC IS IN THE OUTPUT MODE (TCR1.0 = 1).

NOTE 3: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 2.

NOTE 4: TLINK IS PROGRAMMED TO SOURCE THE SA4 BITS.

NOTE 5: TLINK IS PROGRAMMED TO SOURCE THE SA7 AND SA8 BITS.

NOTE 6: SHOWN IS A NON-ALIGN FRAME BOUNDARY.

NOTE 7: SEE Figure 14-3 AND Figure 14-4 FOR DETAILS ON TIMING WITH THE TRANSMIT SIDE ELASTIC STORE ENABLED.

NOTE 1: TSYNC IN THE FRAME MODE (TCR1.1 = 0).

NOTE 2: TSYNC IN THE MULTIFRAME MODE (TCR1.1 = 1).

NOTE 3: TLINK IS PROGRAMMED TO SOURCE ONLY THE Sa4 BIT.

NOTE 4: THIS DIAGRAM ASSEMBLES BOTH THE CAS MF AND THE CRC4 BEGIN WITH THE ALIGN FRAME.

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