DS2153QN-A7 Maxim Integrated, DS2153QN-A7 Datasheet - Page 36
DS2153QN-A7
Manufacturer Part Number
DS2153QN-A7
Description
In Stock
Manufacturer
Maxim Integrated
Datasheet
1.DS2153QA7.pdf
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12 ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION
The DS2153Q provides for access to both the Additional (Sa) and International (Si) bits. On the receive
side, the RAF and RNAF registers will always report the data as it received in the Additional and
International bit locations. The RAF and RNAF registers are updated with the setting of the Receive
Align Frame bit in Status Register 2 (SR2.6). The host can use the SR2.6 bit to know when to read the
RAF and RNAF registers. It has 250µs to retrieve the data before it is lost.
On the transmit side, data is sampled from the TAF and TNAF registers with the setting of the Transmit
Align Frame bit in Status Register 2 (SR2.3). The host can use the SR2.3 bit to know when to update the
TAF and TNAF registers. It has 250µs to update the data or else the old data will be retransmitted. Data
in the Si bit position will be overwritten if either the DS2153Q is programmed: (1) to source the Si bits
from the TSER pin, (2) in the CRC4 mode, or (3) have automatic E-bit insertion enabled. Data in the Sa
bit position will be overwritten if any of the TCR2.3 to TCR2.7 bits are set to 1. See the register
descriptions for TCR1 and TCR2 and the Transmit Data Flow diagram in Section
RAF: RECEIVE ALIGN FRAME REGISTER (Address = 2F Hex)
(MSB)
SYMBOL
Si
Si
0
0
1
1
0
1
1
0
POSITION
RAF.7
RAF.6
RAF.5
RAF.4
RAF.3
RAF.2
RAF.1
RAF.0
0
NAME AND DESCRIPTION
International Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
1
36 of 60
1
0
14
1
for more details.
(LSB)
1
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