ISL8225MIRZ-T Intersil, ISL8225MIRZ-T Datasheet - Page 20

• Manufacturer Part Number: ISL8225MIRZ-T
• Description: ISL8225M Series 20 Vin 1.5 Mhz Dual 15 A Single 30 A Step-Down Power Module
• Manufacturer: Intersil

voltage. Please refer to Table 1 to select the resistor divider for
commonly used conditions. Otherwise, use the following procedures
to finish the EN/FF design:
where:
• R
• N is the total number of the EN/FF pins tied to the resistor divider
Thermal Considerations
The ISL8225M QFN package offers typical junction to ambient
thermal resistance θ
convection (~5.8°C/W at 400LFM) with a typical 4-layer PCB.
Therefore, use Equation 5 to estimate the module junction
temperature:
where:
• T
• T
• P is the total power loss of the module package (W)
• θ
If the calculated temperature, T
design target, the extra cooling scheme is required. Please refer
to “Current Derating” on page 24 for adding air flow.
V
T
R
V
1. A resistor divider from V
2. Check EN turn-on hysteresis (Recommend V
3. Set the maximum current flowing through the top pull-up
4. If the EN/FF is controlled by system EN signal instead of the
5. If the input voltage is below 5.5V, it is recommended to have
6. A 1nF capacitor is recommended on the EN/FF pin to avoid
EN HYS
junction
UP
EN_FTH
ambient
junction
JA
UP
EN/FF voltage between 1.25V to 5.0V. The resistor divider
ratio is recommended to be between 3/1 to 4/1 (as shown in
Figure 21) with a resistor divider at 7.15kΩ/2.05kΩ.
resistor R
ground (V
resistor is used to allow for the input voltage from 5V to 20V
operation. In addition, the maximum current flowing through
R5 is 6.6mA (<7mA).
input voltage, we recommend setting the fixed EN/FF voltage
to about 1/3.5 of the input voltage. If the input voltage is 12V,
a 3.3V system EN signal can be tied to EN/FF pin directly.
EN/FF voltage >1.5V to have better stability. The input voltage
can be directly tied to the VCC pin to disable the internal LDO.
the noise injecting into the feed-forward loop.
–
=
is the thermal resistance of module junction to ambient
is the top resistor of the resistor divider
V EN_HYS
---------------------------- -
I EN_HYS
=
=
=
is the module internal maximum temperature (°C)
is the system ambient temperature (°C)
V
P Θ
N R
UP
EN_RTH
EN/FF
×
•
to below 7mA (considering EN/FF is pulled to
jA
UP
= 0)). Refer to Figure 23; a 3.01kΩ/1kΩ
+
JA
–
•
T
R
ambient
V
3x10
of approximately 10°C/W at natural
DOWN
EN_HYS
IN
–
5
ON/OFF
20
to GND is recommended to set the
=
junction
-------------------------------------------------------------- -
V EN_FTH V EN_REF
FIGURE 26. SIMPLIFIED ENABLE AND VOLTAGE FEED-FORWARD CIRCUIT
R
UP
, is over the required
²
V
–
EN_REF
EN_HYS
R
DOWN
> 0.3V) :
R
UP
ISL8225M
(EQ. 4)
(EQ. 5)
VIN
Functional Description
Initialization
Initially, the Power-On Reset (POR) circuits continuously monitor
bias voltages (V
function initiates soft-start operation 384 clock cycles
after: (1) the EN pin voltage is pulled above 0.8V, (2) all input
supplies exceed their POR thresholds, and (3) the PLL locking
time expires. The Enable pin can be used as a voltage monitor
and to set the desired hysteresis, with an internal 30µA sinking
current going through an external resistor divider. The sinking
current is disengaged after the system is enabled. This feature is
specially designed for applications that require higher input rail
POR for better under-voltage protection. For example, in 12V
applications, R
turn-on threshold (V
(V
During shutdown or fault conditions, soft-start is quickly reset,
and the gate driver immediately changes state (<100ns) when
input drops below POR.
Enable and Voltage Feed-forward
Voltage applied to the EN/FF pin is fed to adjust the sawtooth
amplitude of the channel. Sawtooth amplitude is set to 1.25 times
the corresponding FF voltage when the module is enabled. This
configuration helps maintain a constant gain. This configuration
also helps maintain input voltage to achieve optimum loop response
over a wide input voltage range.
A 384-cycle delay is added after the system reaches its rising
POR and prior to soft-start. The RC timing at the FF pin should be
small enough to ensure that the input bus reaches its static state
and that the internal ramp circuitry stabilizes before soft-start. A
large RC could cause the internal ramp amplitude not to
synchronize with the input bus voltage during output start-up or
when recovering from faults. A 1nF capacitor is recommended as
a starting value for typical applications.
In a multi-module system, with the EN pins are wired together, all
modules can immediately turn off, at one time, when a fault
condition occurs in one or more modules. A fault pulls the EN pin
low, disabling all modules, and does not create current bounce;
thus, no single channel is overstressed when a fault occurs.
Because the EN pins are pulled down under fault conditions, the
pull-up resistor (R
current from the EN pin. Essentially, the EN pins cannot be
directly connected to VCC.
EN
EN_FTH
0.8V
OV, OT, OC, AND PLL LOCKING FAULTS
) to 9V, with 1.6V hysteresis (V
I
EN_HYS
UP
CC
UP
= 53.6kΩ and R
) and voltage at the EN/FF pin. The POR
EN_RTH
= 30µA
) should be scaled to sink no more than 7mA
) to 10.6V and the turn-off threshold
CYCLES
CLOCK
384
DOWN
EN_HYS
= 5.23kΩ sets the
SOFT-START
).
December 3, 2012
FN7822.0