DS87C520-WCL+ Maxim Integrated, DS87C520-WCL+ Datasheet
DS87C520-WCL+
Related parts for DS87C520-WCL+
DS87C520-WCL+ Summary of contents
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... Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers PIN CONFIGURATIONS ...
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... DS87C520-ECL 0˚C to +70˚C DS87C520-ECL+ 0˚C to +70˚C DS87C520-MNL -40˚C to +85˚C DS87C520-MNL+ -40˚C to +85˚C DS87C520-QNL -40˚C to +85˚C DS87C520-QNL+ -40˚C to +85˚C DS87C520-ENL -40˚C to +85˚C DS87C520-ENL+ -40˚C to +85˚C DS87C520-WCL* 0˚C to +70˚C DS83C520-MCL 0˚C to +70˚C DS83C520-MCL+ 0˚ ...
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... The DS83C520 is a factory mask ROM version of the DS87C520 designed for high-volume, cost- sensitive applications identical in all respects to the DS87C520, except that the 16kB of EPROM is replaced by a user-supplied application program. All references to features of the DS87C520 will apply to the DS83C520, with the exception of EPROM-specific features where noted ...
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... Figure 1. Block Diagram DS87C520/ DS83C520 PIN DESCRIPTION PIN DIP PLCC TQFP 22, 23 16, 17 NAME 38 V Positive Supply Voltage. +5V CC GND Digital Circuit Ground Reset Input. The RST input pin contains a Schmitt voltage input to recognize external active high Reset inputs. The pin also ...
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... P1.2 When software writes any port pin, the DS87C520/DS83C520 will activate a strong pulldown that remains on until either written or a reset occurs. Writing a 1 after the port has been at 0 will P1 ...
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... P3.5 T1 P3.6 WR P3.7 RD P3.7 External Access Input, Active Low. Connect to ground to force the DS87C520/DS83C520 to use an external ROM. The internal EA RAM is still accessible as determined by register settings. Connect use internal ROM. CC Not Connected. These pins should not be connected. They are N.C. reserved for use with future devices in this family. ...
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... COMPATIBILITY The DS87C520/DS83C520 are fully static CMOS 8051-compatible microcontrollers designed for high performance. In most cases, the DS87C520/DS83C520 can drop into an existing socket for the 8xc51 family to improve the operation significantly. While remaining familiar to 8051 family users, the devices have many new features. In general, software written for existing 8051-based systems works without modification on the DS87C520/DS83C520 ...
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... SPECIAL FUNCTION REGISTERS Special Function Registers (SFRs) control most special features of the DS87C520/DS83C520. This allows the DS87C520/DS83C520 to have many new features but use the same instruction set as the 8051. When writing software to use a new feature, an equate statement defines the SFR to an assembler or compiler ...
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Table 1. Special Function Register Locations REGISTER BIT 7 BIT 6 P0 P0.7 P0.6 SP DPL DPH DPL1 DPH1 DPS 0 0 PCON SMOD_0 SMOD0 TCON TF1 TR1 TMOD GATE C/T TL0 TL1 TH0 TH1 CKCON WD1 WD0 PORT1 P1.7 ...
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... MEMORY RESOURCES Like the 8051, the DS87C520/DS83C520 use three memory areas. The total memory configuration of the DS87C520/DS83C520 is 16kB of ROM, 1kB of data SRAM and 256 bytes of scratchpad or direct RAM. The 1kB of data space SRAM is read/write accessible and is memory mapped. This on-chip SRAM is reached by the MOVX instruction ...
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... DEFAULT = 16kB DATA MEMORY ACCESS Unlike many 8051 derivatives, the DS87C520/DS83C520 contain on-chip data memory. They also contain the standard 256 bytes of RAM accessed by direct instructions. These areas are separate. The MOVX instruction accesses the on-chip data memory. Although physically on-chip, software treats this area as though it was located off-chip ...
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... When disabled, the 1kB memory area is transparent to the system memory map. Any MOVX directed to the space between 0000h and FFFFh goes to the expanded bus on Ports 0 and 2. This also is the default condition. This default allows the DS87C520/DS83C520 to drop into an existing system that uses these addresses for other hardware and still have full compatibility. ...
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... The timing of block moves of data memory is faster using the Dual Data Pointer (DPTR). The standard 8051 DPTR is a 16-bit value that is used to address off-chip data RAM or peripherals. In the DS87C520/DS83C520, this data pointer is called DPTR0, located at SFR addresses 82h and 83h. These are the original locations. Using DPTR requires no modification of standard code. The new DPTR at SFR 84h and 85h is called DPTR1 ...
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... Power Management Mode offers a complete scheme of reduced internal clock speeds that allow the CPU to run software but to use substantially less power. During default operation, the DS87C520/DS83C520 use four clocks per machine cycle. Thus the instruction cycle rate is Clock/4. At 33MHz crystal speed, the instruction cycle speed is 8 ...
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... CRYSTAL-LESS PMM A major component of power consumption in PMM is the crystal amplifier circuit. The DS87C520/DS83C520 allow the user to switch CPU operation to an internal ring oscillator and turn off the crystal amplifier. The CPU would then have a clock source of approximately 2MHz to 4MHz, divided by either 4, 64, or 1024. The ring is not accurate, so software cannot perform precision timing. However, this mode allows an additional saving of between 0 ...
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... Information in the Status register assists decisions about switching into PMM. This register contains information about the level of active interrupts and the activity on the serial ports. The DS87C520/DS83C520 support three levels of interrupt priority. These levels are Power-fail, High, and Low. Bits STATUS.7-5 indicate the service status of each level. If PIP (Power-fail Interrupt Priority; ...
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... Set the XTOFF bit this time, the crystal oscillation will begin. The DS87C520/DS83C520 then provide a warm-up delay to make certain that the frequency is stable. Hardware will set the XTUP bit (STATUS. when the crystal is ready for use. Then software should write XT begin operating from the crystal ...
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Table 6. PMM Control and Status Bit Summary BIT LOCATION Control. XT runs from crystal or external XT/ RG EXIF.3 clock; XT runs from internal ring oscillator. Status. RGMD = 1, CPU clock = ...
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Figure 3. Invoking and Clearing PMM ...
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... Internally generated interrupts (timer, serial port, Watchdog) are not useful since they require clocking activity. The DS87C520/DS83C520 provide two enhancements to the Stop mode. As documented below, the device provides a bandgap reference to determine Power-Fail Interrupt and Reset thresholds. The default state is that the bandgap reference is off while in Stop mode ...
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The default state is to exit Stop mode without using the ring oscillator. The RGSL - Ring Select bit at EXIF.1 (EXIF; 91h) controls this function. ...
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... CKCON bit is a logic 1, the DS87C520/DS83C520 use 4 clocks per cycle to generate timer speeds. When the bit the DS87C520/DS83C520 use 12 clocks for timer speeds. The reset condition CKCON.5 selects the speed of Timer 2. CKCON.4 selects Timer 1 and CKCON.3 selects Timer 0. ...
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... PFI flag at WDCON.4. A PFI condition sets this bit The flag is independent of the interrupt enable and software must manually clear it. WATCHDOG TIMER To prevent software from losing control, the DS87C520/DS83C520 include a programmable Watchdog Timer. The Watchdog is a free-running timer that sets a flag if allowed to reach a preselected timeout. It can be (re)started by software. ...
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... Watchdog Interrupt using EWDI (EIE.4). The Special Function Register map is shown above. INTERRUPTS The DS87C520/DS83C520 provide 13 interrupt sources with three priority levels. The Power-Fail Interrupt (PFI) has the highest priority. Software can assign high or low priority to other sources. All interrupts that are new to the 8051 family, except for the PFI, have a lower natural priority than the originals ...
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... ROMSIZE.1 ROMSIZE.0 EPROM PROGRAMMING The DS87C520 follows standards for a 16kB EPROM version in the 8051 family available in a UV- erasable, ceramic-windowed package and in plastic packages for one-time user-programmable versions. The part has unique signature information so programmers can support its specific EPROM options. ...
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... P P SECURITY OPTIONS The DS87C520 employs a standard three-level lock that restricts viewing of the EPROM contents. A 64- byte Encryption Array allows the authorized user to verify memory by presenting the data in encrypted form. Lock Bits The security lock consists of three lock bits. These bits select a total of four levels of security. Higher levels provide increasing security but also limit application flexibility ...
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... FFh. Simply programming the array to a non-FFh state will cause the encryption to function. OTHER EPROM OPTIONS The DS87C520 has user selectable options that must be set before beginning software execution. These options use EPROM bits rather than SFRs. Program the EPROM selectable options as shown in Table 9. The Option Register sets or reads these selections ...
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... Figure 5. EPROM Programming Configuration ROM-SPECIFIC FEATURES The DS83C520 supports a subset of the EPROM features found on the DS87C520. SECURITY OPTIONS Lock Bits The DS83C520 employs a lock that restricts viewing of the ROM contents. When set, the lock will prevent MOVC instructions in external memory from reading program bytes in internal memory. When locked, the pin is sampled and latched on reset ...
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DS83C520 ROM VERIFICATION The DS83C520 memory contents can be verified using a standard EPROM programmer. The memory address to be verified is placed on the pins shown in Figure 5, and the programming control pins are set to the levels ...
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... CC A PARAMETER Supply Voltage DS87C520 Power-Fail Warning DS83C520 Minimum Operating DS87C520 Voltage DS83C520 Supply Current Active Mode at 33MHz Supply Current Idle Mode at 33MHz Supply Current Stop Mode, Bandgap Disabled (0°C to +70°C) Supply Current Stop Mode, Bandgap Disabled (-40° ...
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DC ELECTRICAL CHARACTERISTICS (continued 4.5V -40°C to +85°C PARAMETER Transition Current from Ports Input Leakage Port 0, and EA pins, I/O Mode Input Leakage Port 0, ...
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AC ELECTRICAL CHARACTERISTICS (Note 1) PARAMETER External Oscillator Oscillator Frequency External Crystal ALE Pulse Width Port 0 Address Valid to ALE Low Address Hold after ALE Low ALE Low to Valid Instruction In ALE Low to Low PSEN Pulse Width ...
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MOVX CHARACTERISTICS PARAMETER Data Access ALE Pulse Width Port 0 Address Valid to ALE Low Address Hold after ALE Low for MOVX Write RD Pulse Width WR Pulse Width RD Low to Valid Data In Data Hold After Read Data ...
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MOVX CHARACTERISTICS (continued EXTERNAL CLOCK CHARACTERISTICS PARAMETER Clock High Time Clock Low Time ...
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... EXPLANATION OF AC SYMBOLS In an effort to remain compatible with the original 8051 family, the DS87C520 and DS83C520 specify the same parameters as such devices, using the same symbols. For completeness, the following is an explanation of the symbols. t Time A Address C Clock D Input data H Logic level high ...
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EXTERNAL PROGRAM MEMORY READ CYCLE EXTERNAL DATA MEMORY READ CYCLE t AVLL2 ...
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EXTERNAL DATA MEMORY WRITE CYCLE DATA MEMORY WRITE WITH STRETCH = ...
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DATA MEMORY WRITE WITH STRETCH = 2 EXTERNAL CLOCK DRIVE FOUR CYCLE DATA MEMORY WRITE STRETCH VALUE ...
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SERIAL PORT MODE 0 TIMING SERIAL PORT 0 (SYNCHRONOUS MODE) HIGH SPEED OPERATION SM2=1=>TXD CLOCK=XTAL ...
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POWER-CYCLE TIMING EPROM PROGRAMMING AND VERIFICATION WAVEFORMS ...
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PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/DallasPackInfo ...
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PACKAGE INFORMATION (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/DallasPackInfo ...
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PACKAGE INFORMATION (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/DallasPackInfo ...
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PACKAGE INFORMATION (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/DallasPackInfo ...
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... The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation. DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers DESCRIPTION max to from 4 ...