AT89S8253-24JU SL383 Atmel, AT89S8253-24JU SL383 Datasheet - Page 25

• Manufacturer Part Number: AT89S8253-24JU SL383
• Manufacturer: Atmel

Table 14-1.
Notes:
3286P–MICRO–3/10
SPCR Address = D5H
Not Bit Addressable
Symbol
SPIE
SPE
DORD
MSTR
CPOL
CPHA
SPR0
SPR1
Bit
1. Set up the clock mode before enabling the SPI: set all bits needed in SPCR except the SPE bit, then set SPE.
2. Enable the master SPI prior to the slave device.
3. Slave echoes master on next Tx if not loaded with new data.
SPIE
Function
SPI interrupt enable. This bit, in conjunction with the ES bit in the IE register, enables SPI interrupts: SPIE = 1 and ES = 1
enable SPI interrupts. SPIE = 0 disables SPI interrupts.
SPI enable. SPI = 1 enables the SPI channel and connects SS, MOSI, MISO and SCK to pins P1.4, P1.5, P1.6, and P1.7.
SPI = 0 disables the SPI channel.
Data order. DORD = 1 selects LSB first data transmission. DORD = 0 selects MSB first data transmission.
Master/slave select. MSTR = 1 selects Master SPI mode. MSTR = 0 selects slave SPI mode.
Clock polarity. When CPOL = 1, SCK is high when idle. When CPOL = 0, SCK of the master device is low when not
transmitting. Please refer to figure on SPI clock phase and polarity control.
Clock phase. The CPHA bit together with the CPOL bit controls the clock and data relationship between master and slave.
Please refer to figure on SPI clock phase and polarity control.
SPI clock rate select. These two bits control the SCK rate of the device configured as master. SPR1 and SPR0 have no
effect on the slave. The relationship between SCK and the oscillator frequency, F
7
SPCR – SPI Control Register
SPR1SPR0SCK
00f/4 (f/2 in x2 mode)
01f/16 (f/8 in x2 mode)
10f/64 (f/32 in x2 mode)
11f/128 (f/64 in x2 mode)
SPE
6
DORD
5
MSTR
4
CPOL
3
CPHA
2
OSC.
, is as follows:
Reset Value = 0000 0100B
SPR1
1
AT89S8253
SPR0
0
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