AT89S8253-24JU SL383 Atmel, AT89S8253-24JU SL383 Datasheet - Page 12

• Manufacturer Part Number: AT89S8253-24JU SL383
• Manufacturer: Atmel

8. Programmable Watchdog Timer
12
AT89S8253
The programmable Watchdog Timer (WDT) counts instruction cycles. The prescaler bits, PS0,
PS1 and PS2 in SFR WDTCON are used to set the period of the Watchdog Timer from 16K to
2048K instruction cycles. The available timer periods are shown in
period is dependent upon the external clock frequency.
The WDT is disabled by Power-on Reset and during Power-down mode. When WDT times out
without being serviced or disabled, an internal RST pulse is generated to reset the CPU. See
Table 8-1
Table 8-1.
PS2
for the WDT period selections.
0
0
0
0
1
1
1
1
Watchdog Timer Time-out Period Selection
WDT Prescaler Bits
PS1
0
0
1
1
0
0
1
1
PS0
0
1
0
1
0
1
0
1
Table
Period (Nominal for
F
CLK
8-1.
1024 ms
2048 ms
128 ms
256 ms
512 ms
16 ms
32 ms
64 ms
= 12 MHz)
The WDT time-out
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