IS61C512-35TI ETC-unknow, IS61C512-35TI Datasheet - Page 7

• Manufacturer Part Number: IS61C512-35TI
• Description: 64k X 8 High-speed Cmos Static Ram
• Manufacturer: ETC-unknow

WRITE CYCLE NO. 2 (CE1
IS61C512
Notes:
1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
2. I/O will assume the High-Z state if OE = HIGH.
Integrated Circuit Solution Inc.
SR011-0B
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
ADDRESS
D
CE1
CE2
OUT
WE
D
IN
CE1
CE1
CE1
CE1, CE2 Controlled)
DATA UNDEFINED
t
SA
t
HZWE
t
AW
t
SCE1
t
(1,2)
SCE2
t
PWE
t
WC
HIGH-Z
t
SD
DATA-IN VALID
t
HA
t
t
HD
LZWE
7