IS61C512-35TI ETC-unknow, IS61C512-35TI Datasheet
IS61C512-35TI
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IS61C512-35TI Summary of contents
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... CMOS input levels. Easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS61C512 is available in 32-pin 300mil DIP, SOJ and 8*20mm TSOP-1 packages. DECODER MEMORY ARRAY ...
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... IS61C512 PIN CONFIGURATION 32-Pin DIP and SOJ VCC A15 A14 3 30 CE2 A12 A13 A11 A10 CE1 I/O7 I/ I/O6 I/ I/O5 I/ I/O4 GND 16 17 I/O3 PIN DESCRIPTIONS A0-A15 Address Inputs ...
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... IS61C512 OPERATING RANGE Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C DC ELECTRICAL CHARACTERISTICS Symbol Parameter V Output HIGH Voltage OH V Output LOW Voltage OL V Input HIGH Voltage IH (1) V Input LOW Voltage IL I Input Leakage LI I Output Leakage LO Notes – ...
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... IS61C512 READ CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Read Cycle Time RC t Address Access Time AA t Output Hold Time OHA CE1 Access Time t 1 ACE t CE2 Access Time ACE 2 OE Access Time t DOE OE to Low-Z Output (2) t LZOE OE to High-Z Output (2) t HZOE ...
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... IS61C512 AC WAVEFORMS READ CYCLE NO. 1 (1,2) ADDRESS D OUT READ CYCLE NO. 2 (1,3) ADDRESS OE CE1 CE2 D OUT SUPPLY CURRENT Notes HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE1 = V 3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions. Integrated Circuit Solution Inc. ...
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... IS61C512 WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Write Cycle Time WC CE1 to Write End t 1 SCE t CE2 to Write End 2 SCE t Address Setup Time to Write End AW t Address Hold from Write End HA t Address Setup Time SA WE Pulse Width (4) t PWE t Data Setup to Write End ...
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... IS61C512 WRITE CYCLE NO. 2 (CE1 CE1 CE1 CE1, CE2 Controlled) CE1 ADDRESS CE1 CE2 WE D OUT D IN Notes: 1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write ...
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... TSOP-1 IS61C512-25JI 300mil SOJ IS61C512-25NI 300mil DIP IS61C512-25TI 8*20mm TSOP-1 IS61C512-35JI 300mil SOJ IS61C512-35NI 300mil DIP IS61C512-35TI 8*20mm TSOP-1 Integrated Circuit Solution Inc. HEADQUARTER: HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: TH TEL: 886-2-26962140 FAX: 886-2-26962252 http://www ...