LC51024MV-75F484I Lattice Semiconductor, LC51024MV-75F484I Datasheet - Page 26

• Manufacturer Part Number: LC51024MV-75F484I
• Description: CPLD ispXPLD? 5000MV Family 300K Gates 1024 Macro Cells 200MHz Industrial EECMOS Technology 3.3V 484-Pin FPBGA
• Manufacturer: Lattice Semiconductor

Lattice Semiconductor
sysIO Recommended Operating Conditions
LVCMOS 3.3
LVCMOS 2.5
LVCMOS 1.8
LVTTL
PCI 3.3
AGP-1X
SSTL 2
SSTL 3
CTT 3.3
CTT 2.5
HSTL Class I
HSTL Class III
HSTL Class IV
GTL+
LVDS
1. Design tools default setting.
2. Inputs are independent of V
Standard
1
Min.
1.65
3.15
3.0
2.3
3.0
3.0
2.3
3.0
3.0
2.3
1.4
1.4
1.4
1.4
2.3
CCO
setting. However, V
V
CCO
2.5/3.3
Typ.
3.3
2.5
1.8
3.3
3.3
3.3
2.5
3.3
3.3
2.5
1.5
1.5
1.5
—
(V)
CCO
2
must be set within the valid operating range for one of the supported standards.
Max.
1.95
3.45
3.6
2.7
3.6
3.6
2.7
3.6
3.6
2.7
1.6
1.6
1.6
3.6
3.6
26
ispXPLD 5000MX Family Data Sheet
0.882
Min.
1.15
1.35
1.35
0.68
1.3
—
—
—
—
—
—
—
—
—
V
REF
Typ.
1.25
0.75
1.5
1.5
1.5
0.9
0.9
1.0
—
—
—
—
—
—
—
(V)
1.122
Max.
1.35
1.65
1.65
1.7
0.9
—
—
—
—
—
—
—
—
—