TDK5110FHTMA1 Infineon, TDK5110FHTMA1 Datasheet - Page 11

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TDK5110FHTMA1

Manufacturer Part Number
TDK5110FHTMA1
Description
Transmitter Ask/Fsk Sgl Tssop10
Manufacturer
Infineon
Datasheet
Wireless Components
8
9
10
11
12
FSKGND
CLKOUT
FSKOUT
CLKDIV
COSC
9
60 k
V
V
S
S
200 µA
6 k
1.5 k
300
+1.2 V
60 k
11
12
100 A
10
8
V
S
5 A
3 - 5
+0.8 V
Clock output to supply an external device.
An external pull-up resistor has to be added
in accordance to the driving requirements of
the external device.
A clock frequency of 3.39 MHz is selected
by a logic low at CLKDIV input (pin 9).
A clock frequency of 847.5 kHz is selected
by a logic high at CLKDIV input (pin 9).
This pin is used to select the desired clock
division rate for the CLKOUT signal.
A logic low (CLKDIV < 0.2 V) applied to this
pin selects the 3.39 MHz output signal at
CLKOUT (pin 8).
A logic high (CLKDIV open) applied to this
pin selects the 847.5 kHz output signal at
CLKOUT (pin 8).
This pin is connected to the reference oscil-
lator circuit.
The reference oscillator is working as a neg-
ative impedance converter. It presents a
negative resistance in series to an induc-
tance at the COSC pin.
This pin is connected to a switch to
FSKGND (pin 12).
The switch is closed when the signal at
FSKDTA (pin 7) is in a logic low state.
The switch is open when the signal at
FSKDTA (pin 7) is in a logic high state.
FSKOUT can switch an additional capacitor
to the reference crystal network to pull the
crystal frequency by an amount resulting in
the desired FSK frequency shift of the trans-
mitter output frequency.
Ground connection for FSK modulation out-
put FSKOUT.
Specification, October 2002
Functional Description
TDK 5110

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