ADC10662CIWMX/NOPB National Semiconductor, ADC10662CIWMX/NOPB Datasheet - Page 13

• Manufacturer Part Number: ADC10662CIWMX/NOPB
• Manufacturer: National Semiconductor

www.national.com
Functional Description
SIMILAR PRODUCT DIFFERENCES
The ADC1006x, ADC1046x and ADC1066x (where "x" indi-
cates the number of multiplexer inputs) are similar devices
with different specification limits. The differences in these
device families are summarized below.
Applications Information
1.0 MODES OF OPERATION
The ADC10662 and ADC10664 have two basic digital inter-
face modes. Figure 1 and Figure 2 are timing diagrams for
the two modes. The ADC10662 and ADC10664 have input
multiplexers that are controlled by the logic levels on pins S
and S
tables showing how the input channels are assigned.
Mode 1
In this mode, the S/H pin controls the start of conversion. S/H
is pulled low for a minimum of 150 ns. This causes the
comparators in the “coarse” flash converter to become ac-
tive. When S/H goes high, the result of the coarse conver-
sion is latched and the “fine” conversion begins. After 360 ns
(typical), INT goes low, indicating that the conversion results
are latched and can be read by pulling RD low. Note that CS
must be low to enable S/H or RD. CS is internally “ANDed”
with S/H and RD; the input voltage is sampled when CS and
S/H are low, and data is read when CS and RD are low. INT
is reset high on the rising edge of RD.
Mode 2
In Mode 2, also called “RD mode”, the S/H and RD pins are
tied together. A conversion is initiated by pulling both pins
low. The A/D converter samples the input voltage and
causes the coarse comparators to become active. An inter-
nal timer then terminates the coarse conversion and begins
the fine conversion. 470 ns (typical) after S/H and RD are
Device
Family
ADC1006x
ADC1046x
ADC1066x
1
TABLE 1. Input Multiplexer Programming
TABLE 2. Input Multiplexer Programming
when S/H goes low. Table 1 and Table 2 are truth
S
0
0
1
1
1
S
0
1
0
Guaranteed
ILE, TUE,
PSS
-
-
ADC10664
ADC10662
S
0
1
0
1
0
V
V
IN0
IN1
Guaranteed
Guaranteed
THD, SNR,
ENOB
-
V
V
V
V
IN0
IN1
IN2
IN3
Channel
(Continued)
Channel
Conversion
900ns
900ns
466ns
Time
Max.
0
12
pulled low, INT goes low, indicating that the conversion is
completed. Approximately 20 ns later the data appearing on
the TRI-STATE output pins will be valid. Note that data will
appear on these pins throughout the conversion, but until
INT goes low the data at the output pins will be the result of
the previous conversion.
2.0 REFERENCE CONSIDERATIONS
The ADC10662 and ADC10664 each have two reference
inputs. These inputs, V
and define the zero to full-scale range of the input signal.
The reference inputs can be connected to span the entire
supply voltage range (V
metric applications, or they can be connected to different
voltages (as long as they are between ground and V
when other input spans are required.
Reducing the overall V
the sensitivity of the converter (e.g., if V
= 1.953 mV). Note, however, that linearity and offset errors
become larger when lower reference voltages are used. See
the Typical Performance Curves for more information. For
this reason, reference voltages less than 2V are not recom-
mended.
In most applications, V
ground, but it is often useful to have an input span that is
offset from ground. This situation is easily accommodated by
the reference configuration used in the ADC10662 and
ADC10664. V
ground as long as the voltage source connected to this pin is
capable of sinking the converter’s reference current (12.5
mA Max
other than ground, bypass it with multiple capacitors.
Since the resistance between the two reference inputs can
be as low as 400Ω, the voltage source driving the reference
inputs should have low output impedance. Any noise on
either reference input is a potential cause of conversion
errors, so each of these pins must be supplied with a clean,
low noise voltage source. Each reference pin should be
bypassed with a 10 µF tantalum and a 0.1 µF ceramic.
3.0 THE ANALOG INPUT
The ADC10662 and ADC10664 sample the analog input
voltage once every conversion cycle. When this happens,
the input is briefly connected to an impedance approximately
equal to 600Ω in series with 35 pF. Short-duration current
spikes can be observed at the analog input during normal
operation. These spikes are normal and do not degrade the
converter’s performance.
Large source impedances can slow the charging of the
sampling capacitors and degrade conversion accuracy.
Therefore, only signal sources with output impedances less
than 500Ω should be used if rated accuracy is to be
achieved at the minimum sample time (250 ns maximum). If
the sampling time is increased, the source impedance can
be larger. If a signal source has a high output impedance, its
output should be buffered with an operational amplifier. The
operational amplifier’s output should be well-behaved when
driving a switched 35 pF/600Ω load. Any ringing or voltage
shifts at the op-amp’s output during the sampling period can
result in conversion errors.
Correct conversion results will be obtained for input voltages
greater than GND − 50 mV and less than V
allow the signal source to drive the analog input pin beyond
@
V
REF
REF−
= 5V). If V
can be connected to a voltage other than
REF+
REF
REF−
REF−
span to less than 5V increases
REF−
and V
= 0V, V
will simply be connected to
is connected to a voltage
REF−
REF+
REF
, are fully differential
+
= V
= 2V, then 1 LSB
+ 50 mV. Do not
CC
) for ratio-
CC
)