S8865-128G HAMAMATSU [Hamamatsu Corporation], S8865-128G Datasheet - Page 6

• Manufacturer Part Number: S8865-128G
• Description: Photodiode array combined with signal processing IC for X-ray detection
• Manufacturer: HAMAMATSU [Hamamatsu Corporation]

1. The internal timing circuit starts operation at the falling edge of CLK immediately after a RESET pulse goes Low.
2. When the falling edge of each CLK is counted as “1 clock”, the video signal of the 1st channel appears between “18.5 clocks and 20.5
3. To obtain video signals, extend the High period 3 clocks from the falling edge of CLK immediately after the RESET pulse goes Low, to a
4. The trigger pulse for the 1st channel rises at a timing of 19.5 clocks and then rises every 4 clocks. The rising edge of each trigger pulse
5. Signal charge integration time equals the High period of a RESET pulse. However, the charge integration does not start at the rise of
6. The video signal after an EOS signal output becomes a high impedance state, and the video output will be inde nite.
Clock pulse width
Clock pulse rise/fall times
Reset pulse width 1
Reset pulse width 2
Reset pulse rise/fall times
Clock pulse-reset pulse timing 1
Clock pulse-reset pulse timing 2
clocks”. Subsequent video signals appear every 4 clocks.
20 clock period.
is the recommended timing for data acquisition.
a RESET pulse but starts at the 8th clock after the rise of the RESET pulse and ends at the 8th clock after the fall of the RESET pulse.
After the RESET pulse next changes from High to Low, signals integrated within this period are sequentially read out as time-series
signals by the shift register operation. The rise and fall of a RESET pulse must be synchronized with the rise of a CLK pulse, but the rise
of a RESET pulse must be set outside the video output period. One cycle of RESET pulses cannot be set shorter than the time equal to
“36.5 + 4 × N (number of elements)” clocks.
CLK
RESET
Video
Trig
EOS
tpw(CLK1)
tf(CLK)
1 2 3
Photodiode arrays with ampli er
tf(RESET)
tpw(RESET1)
Parameter
t1
20 clocks
tr(CLK)
4 5 14 15 16 17
Video output
period
tpw(RESET1)
8 clocks
18 19 20
1
tpw (CLK1), tpw (CLK2)
tr (RESET), tf (RESET)
S8866-64G-02
t2
tr(RESET)
tr (CLK), tf (CLK)
2
tpw (RESET1)
tpw (RESET2)
tpw(RESET2)
tpw(RESET2)
Symbol
t1
t2
n-1
n
S8865-64G/-128G/-256G, S8866-64G-02/-128G-02
Integration time
Min.
500
-20
-20
15
20
0
0
Typ.
20
20
0
0
-
-
-
1 2 3
8 clocks
12500
Max.
30
30
20
20
-
-
KMPDC0278EB
Unit
ns
ns
ns
ns
ns
s
s
6