UT54ACS109 AEROFLEX [Aeroflex Circuit Technology], UT54ACS109 Datasheet

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UT54ACS109

Manufacturer Part Number
UT54ACS109
Description
Radiation-Hardened Dual J-K Flip-Flops
Manufacturer
AEROFLEX [Aeroflex Circuit Technology]
Datasheet
61
UT54ACS109/UT54ACTS109
Radiation-Hardened
Dual J-K Flip-Flops
FEATURES
• High speed
• Low power consumption
• Single 5 volt supply
• Available QML Q or V processes
• Flexible package
DESCRIPTION
The UT54ACS109 and the UT54ACTS109 are dual J-K posi-
tive triggered flip-flops. A low level at the preset or clear inputs
sets or resets the outputs regardless of the other input levels.
When preset and clear are inactive (high), data at the J and K
input meeting the setup time requirements are transferred to the
outputs on the positive-going edge of the clock pulse. Following
the hold time interval, data at the J and K input can be changed
without affecting the levels at the outputs. The flip-flops can
perform as toggle flip-flops by grounding K and tying J high.
They also can perform as D flip-flops if J and K are tied together.
The devices are characterized over full military temperature
range of -55 C to +125 C.
FUNCTION TABLE
Note:
1. The output levels in this configuration are not guaranteed to meet the mini-
mum levels for V
addition, this configuration is nonstable; that is, it will not persist when either
preset or clear returns to its inactive (high) level.
- Latchup immune
- 16-pin DIP
- 16-lead flatpack
PRE
H
H
H
H
H
H
L
L
radiation-hardened CMOS
OH
CLR
H
H
H
H
H
H
if the lows at preset and clear are near V
L
L
INPUTS
CLK
X
X
X
L
X
X
X
H
H
X
J
L
L
K
X
X
X
H
H
X
L
L
IL
H
No Change
No Change
Q
H
H
maximum. In
OUTPUT
L
L
1
Toggle
H
Q
H
H
L
L
1
PINOUTS
LOGIC SYMBOL
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and
IEC Publication 617-12.
CLR1
CLK1
PRE1
V
K1
Q1
Q1
PRE1
CLK1
CLR1
PRE2
CLK2
CLR2
J1
SS
K1
K2
J1
J2
(13)
(15)
(2)
(4)
(11)
(14)
(12)
(5)
(3)
(1)
CLR1
CLK1
PRE1
V
K1
Q1
Q1
SS
J
16-Lead Flatpack
S
J1
K1
R
C1
16-Pin DIP
Top View
Top View
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
16
15
14
13
12
11
10
9
9
V
CLR2
J2
K2
CLK2
PRE2
Q2
Q2
DD
RadHard MSI Logic
(10)
(6)
(7)
(9)
Q1
Q1
Q2
Q2
V
CLR2
J2
K2
CLK2
PRE2
Q2
Q2
DD

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UT54ACS109 Summary of contents

Page 1

... DIP - 16-lead flatpack DESCRIPTION The UT54ACS109 and the UT54ACTS109 are dual J-K posi- tive triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the other input levels. When preset and clear are inactive (high), data at the J and K input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse ...

Page 2

... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RadHard MSI Logic 1 LIMIT 1.0E6 80 120 1.0E14 PARAMETER Supply voltage Voltage any pin Storage Temperature range Maximum junction temperature DC input current Maximum power dissipation UT54ACS109/UT54ACTS109 Q Q UNITS rads(Si) 2 MeV-cm /mg 2 MeV-cm /mg 2 n/cm LIMIT UNITS -0 ...

Page 3

... UT54ACS109/UT54ACTS109 RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER Supply voltage Input voltage any pin Temperature range LIMIT UNITS 4 125 C RadHard MSI Logic ...

Page 4

... 50pF 5.5V DD For input under test For all other inputs 5. 1MHz @ 1MHz @ 0V UT54ACS109/UT54ACTS109 MIN MAX 0.8 .3V . 0.40 0.25 . 0.25 DD and V -200 200 0.4V 2.0 1.6 - 2.1V ...

Page 5

... UT54ACS109/UT54ACTS109 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to V (min) and V (max) ...

Page 6

... All specifications valid for radiation dose 1E6 rads(Si). 3. Based on characterization, hold time ( 0ns can be assumed if data setup time (t H RadHard MSI Logic 2 < +125 C) C PARAMETER ) is >10ns. This is guaranteed, but not tested. SU2 UT54ACS109/UT54ACTS109 MINIMUM MAXIMUM ...

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