P620-30DC PLL [PhaseLink Corporation], P620-30DC Datasheet

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P620-30DC

Manufacturer Part Number
P620-30DC
Description
PECL and LVDS Low Phase Noise XO (32.5 to 130MHz output)
Manufacturer
PLL [PhaseLink Corporation]
Datasheet
FEATURES
DESCRIPTION
The PLL620-30 is a XO IC specifically designed to
drive fundamental or 3
130MHz, with selectable PECL or LVDS outputs and
OE logic (enable high or enable low). Its design was
optimized to tolerate higher limits of interelectrode
capacitance and bonding capacitance to improve
yield. It achieves very low current into the crystal
resulting in better overall stability.
DIE SPECIFICATIONS
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/09/04 Page 1
XOUT
XIN
Pad dimensions
65MHz to 130MHz Crystal input.
Output range: 32.5MHz – 130MHz (no PLL).
Low Injection Power for crystal, 50uW.
Complementary outputs: PECL or LVDS.
Selectable OE Logic
Supports 2.5V or 3.3V-Power Supply.
Available in die form.
Thickness 10 mil.
Reverse side
Thickness
Name
Size
Oscillator
Amplifier
PECL and LVDS Low Phase Noise XO (32.5 to 130MHz output)
rd
OT crystals from 65MHz to
80 micron x 80 micron
62 x 65 mil
Value
10 mil
PLL620-30
GND
OE
Q
Q
DIE CONFIGURATION
OUTPUT SELECTION AND ENABLE
Pad #9, #25: Bond to GND to set to “0”. Internal pull up.
Pad #30: Logical states defined by PECL levels if OESEL is “1”
OUTPUT FREQUENCY SELECTOR
*Internally set to ‘Default’ through 60K
Y
1 (default)
(Pad #25)
XOUT
CTRL
OESEL
XIN
N/C
S2^
N/C
OE
X
(0,0)
0
1(Default)*
OUTSEL
(Pad #9)
Logical states defined by CMOS levels if OESEL is “0”
26
27
28
29
30
31
S2
25
0
1
0
1
(Pad #30)
OE_CTRL
C502A
A2020-20A
24
2
Die ID:
0
1
0
1
23
3
22
4
LVDS
PECL (default)
21
Tri-state
Output enabled (default)
Output enabled (default)
Tri-state
5
65 mil
PLL620-30
Selected Output
20
6
pull-up resistor
19
State
Output
Input/2
7
Input
18
8
10
12
11
16
15
14
13
(1550,1475)
17
9
GNDBUF
N/C
LVDSB
PECLB
VDDBUF
VDDBUF
PECL
LVDS
OUTSEL^

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P620-30DC Summary of contents

Page 1

PECL and LVDS Low Phase Noise XO (32.5 to 130MHz output) FEATURES • 65MHz to 130MHz Crystal input. • Output range: 32.5MHz – 130MHz (no PLL). • Low Injection Power for crystal, 50uW. • Complementary outputs: PECL or LVDS. • ...

Page 2

PECL and LVDS Low Phase Noise XO (32.5 to 130MHz output) ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human ...

Page 3

PECL and LVDS Low Phase Noise XO (32.5 to 130MHz output) 6. LVDS Electrical Characteristics PARAMETERS Output Differential Voltage V Magnitude Change DD Output High Voltage Output Low Voltage Offset Voltage Offset Magnitude Change Power-off Leakage Output Short Circuit Current ...

Page 4

PECL and LVDS Low Phase Noise XO (32.5 to 130MHz output) 8. PECL Electrical Characteristics PARAMETERS SYMBOL Output High Voltage Output Low Voltage 9. PECL Switching Characteristics PARAMETERS Clock Rise Time Clock Fall Time PECL Levels Test Circuit OUT 50Ω ...

Page 5

PECL and LVDS Low Phase Noise XO (32.5 to 130MHz output) PAD ASSIGNMENT Pad # Name 1 Optional GND 2 Optional GND 3 Optional GND 4 Optional GND 5 GND 6 Reserved 7 Optional GNDBUF 8 GNDBUF 9 OUTSEL 10 ...

Page 6

... President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/09/04 Page 6 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER PLL620- Marking P620-30DC PLL620-30 TEMPERATURE C=COMMERCIAL I=INDUSTRIAL PACKAGE TYPE D=DIE Package Option Die – ...

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