P620-21DC PLL [PhaseLink Corporation], P620-21DC Datasheet

P620-21DC

Manufacturer Part Number

P620-21DC

Description

Low Phase Noise XO (for HF Fund. and 3-rd O.T.)

Manufacturer

PLL [PhaseLink Corporation]

Datasheet

1.P620-21DC.pdf (7 pages)

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FEATURES

•

DESCRIPTIONS

PLL620-21 is an XO IC specifically designed to work

with high frequency fundamental and third overtone

crystals. Its design was optimized to tolerate higher

limits of interelectrodes capacitance and bonding

capacitance to improve yield. It achieves very low

current into the crystal resulting in better overall

stability. It offers a selectable OE logic and is ideal

for XO applications requiring LVDS or PECL output

levels at high frequencies.

BLOCK DIAGRAM

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 07/15/05 Page 1

100MHz to 200MHz Fundamental Mode Crystal.

Output range: 100 – 200MHz (no multiplication).

Selectable OE logic.

Minimum bondwires required for VDD and GND.

Available outputs: PECL or LVDS.

Supports 3.3V-Power Supply.

Available in die form.

Thickness 10 mil.

)0 1 23 *

4 5 *

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Low Phase Noise XO (for HF Fund. and 3

DIE CONFIGURATION

DIE SPECIFICATIONS

OUTPUT SELECTION AND ENABLE

Pad # 9:

Pad # 30: Logical states defined by PECL levels if OUTSEL (pad # 9) is “1”

Pad #25

(default)

OESEL

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Pad dimensions

Reverse side

Bond to GND to set to “0”, bond to VDD to set to “1”

Logical states defined by CMOS levels if OUTSEL is “0”

Thickness

OUTSEL

Pad #9

Name

Size

OE_CTRL

Pad #30

Preliminary

LVDS

PECL (default)

Tri-state

Output enabled (default)

Tri-state

80 micron x 80 micron

PLL620-21

Selected Output

62 x 65 mil

10 mil

Value

State

GND

O.T.)

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