P620-05OC ETC1 [List of Unclassifed Manufacturers], P620-05OC Datasheet

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P620-05OC

Manufacturer Part Number
P620-05OC
Description
Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal)
Manufacturer
ETC1 [List of Unclassifed Manufacturers]
Datasheet
FEATURES
DESCRIPTION
The PLL620-0x family of XO IC’s is specifically
designed to work with high frequency fundamental
and third overtone crystals. Their low jitter and low
phase noise performance make them well suited for
high frequency XO requirements. They achieve very
low current into the crystal resulting in better overall
stability.
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/01/05 Page 1
SEL
X+
X-
100MHz to 200MHz Fundamental or 3
Overtone Crystal.
Output range: 100 – 200MHz (no multiplication),
200 – 400MHz (2x multiplier), 400 – 700MHz (4x
multiplier), or 800MHz-1GHz(PLL620-09 only, 8x
multiplier).
CMOS (Standard drive PLL620-07 or Selectable
Drive PLL620-06), PECL (Enable low PLL620-08
or Enable high PLL620-05) or LVDS output
(PLL620-09).
Supports 3.3V-Power Supply.
Available in 16-Pin (TSSOP or 3x3mm QFN)
Note: PLL620-06 only available in 3x3mm.
Note: PLL620-07 only available in TSSOP.
Oscillator
Amplifier
Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal)
PLL by-pass
(Phase
Locked
Loop)
PLL
rd
OE
Q
Q
PLL620-05/-06/-07/-08/-09
^: Internal pull-up
*: PLL620-06 pin 12 is output drive select (DRIVSEL)
OUTPUT ENABLE LOGICAL LEVELS
OE input: Logical states defined by PECL levels for PLL620-08
The pin remains ‘Do Not Connect (DNC)’ for PLL620-05/07/08/09.
(0 for High Drive CMOS, 1 for Standard Drive CMOS)
PLL620-08
PLL620-05
PLL620-06
PLL620-07
PLL620-09
Part #
Logical states defined by CMOS levels for PLL620-05/-06/-
07/-09
SEL2^
XOUT
SEL3^
SEL2^
PIN CONFIGURATION
XOUT
GND
GND
VDD
XIN
OE
XIN
OE
(Default)
(Default)
OE
(Top View)
0
1
0
1
14
15
13
16
1
2
3
4
5
6
7
8
Universal Low Phase Noise IC’s
12
PLL620-0x
1
11
2
Output enabled
Tri-state
Tri-state
Output enabled
10
3
9
4
16
15
14
13
12
11
10
9
8
7
6
5
State
SEL0^
SEL1^
GND
CLKC
VDD
CLKT
GND
GND
GND
CLKC
VDD
CLKT

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P620-05OC Summary of contents

Page 1

Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal) FEATURES • 100MHz to 200MHz Fundamental or 3 Overtone Crystal. • Output range: 100 – 200MHz (no multiplication), 200 – 400MHz (2x multiplier), 400 – 700MHz (4x multiplier), ...

Page 2

Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal) PIN DESCRIPTIONS TSSOP* Name Pin number VDD 1, 12 XIN 2 XOUT GND 7,8,9, 10, 14 DRIVSEL** - CLKT 11 CLKC 13 SEL0 16 SEL1 ...

Page 3

Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal) ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, ...

Page 4

Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal) 4. Jitter Specifications PARAMETERS Period jitter RMS Period jitter peak-to-peak Accumulated jitter RMS Accumulated jitter peak-to-peak Random Jitter Integrated jitter RMS at 155MHz Period jitter RMS Period jitter ...

Page 5

Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal) 7. LVDS Electrical Characteristics PARAMETERS Output Differential Voltage V Magnitude Change DD Output High Voltage Output Low Voltage Offset Voltage Offset Magnitude Change Power-off Leakage Output Short Circuit ...

Page 6

Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal) 9. PECL Electrical Characteristics PARAMETERS SYMBOL Output High Voltage Output Low Voltage 19. PECL Switching Characteristics PARAMETERS Clock Rise Time Clock Fall Time PECL Levels Test Circuit OUT ...

Page 7

Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal) PACKAGE INFORMATION 16 PIN TSSOP ( mm ) Symbol Min. Max 1.20 A1 0.05 0.15 B 0.19 0.30 C 0.09 0.20 D 4.90 5.10 E 4.30 ...

Page 8

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